Bridging the Boundaries: Wafer, Panel and Beyond
October 13 - 15, 2020
DoubleTree by Hilton San Jose
San Jose, California, USA

IWLPC Technical Committee

If you are interested in being part of the technical committee, contact IWLPC, iwlpc@iwlpc.com or +1-952-920-7682.

3D Integration

John Lannon

Chair: John Lannon, Ph.D., Micross Advanced Interconnect Technology

Dr. John Lannon is the General Manager of Micross Advanced Interconnect Technology, a business unit of Micross focused on wafer-level advanced packaging, interconnect, and device integration technologies. Since receiving his Ph.D. degree in Physics from WVU in 1996, he has worked on the development of thin film materials and advanced packaging processes (e.g. high density interconnects, TSV integration, and wafer-level vacuum packaging) for next generation microsystems in sensor and scene projector applications.




Thomas Gregorich

Thomas Gregorich, ZEISS Semiconductor Manufacturing Technology

Thomas Gregorich is Director of Business Development at ZEISS Semiconductor Manufacturing Technology where he is responsible for 3D measurement and characterization products marketed by the Advanced Packaging Business Unit. Previously Mr. Gregorich held senior-level positions at Western Digital, Micron and Qualcomm, and has extensive experience in the development and commercialization of advanced 3D IC packages. Prior to his position at Qualcomm, Mr. Gregorich worked for Motorola and had assignments in the Semiconductor Products Sector and Corporate Research, in the United States as well as in Japan, Taiwan and China. Mr. Gregorich has a BS in Mechanical Engineering from Bradley University, an MBA from Northern Illinois University and is a Senior Member of IEEE.




Zia Karim, Ph.D.

Zia Karim, Ph.D., Yield Engineering Systems

Zia Karim, an IEEE Sr. Member, is currently Sr. Vice President and Chief Marketing Officer at Yield Engineering Systems, a leading Semiconductor Equipment Company for Backend Advanced Packaging Processes. Dr. Karim most recently was Vice President of Business Development and Technology at AIXTRON/Genus (acquisitions) where he worked for over 15 years. Dr. Karim has held senior management positions in Applied Materials, and Novellus after he started his career in Sharp Microelectronics in 1994. Dr. Karim received Ph.D, in Electronic Engineering from Dublin City University in Ireland, and B.Sc and M.Sc degree from Bangladesh University of Engineering and Technology in Electrical and Electronic Engineering. Dr. Karim took a pioneering role in positioning W/WSi CVD, Low k PECVD, High K ALD, and III-V MOCVD process in Semiconductor Logic and Memory Devices. Dr. Karim organized and moderated “III-V on Si” Seminars jointly with Sematech at every pre-IEDM from 2006 to 2012. Dr. Karim owns fourteen (14) patents. Other than Organizing or co-organizing several Conference Symposiums and related Transactions, Dr. Karim also authored more than forty (40) published papers in peer-reviewed journals, as well as provided several Invited talks.




Herb Reiter, eda 2 asic Consulting, Inc.

After more than 20 years in technical and business roles at ASIC vendors and EDA software companies, Herb founded eda2asic Consulting, Inc. in 2002. Initially he focused on business development work to introduce products and services developed by mostly smaller EDA firms to major ASIC vendors. He introduced tools and IP for simplifying and accelerating SoC design efforts for integrating single die solutions into IC packages. Herb earned MSEE and MBA degrees in Austria/Europe, an MBA at San Jose State University and has attended 40+ Continuing Education Classes at Stanford University.




Ted Tessier

Ted Tessier, Gordian Semiconductor Packaging Solutions

Ted is the Founder and Chief Technologist of Gordian Semiconductor Packaging Solutions, a subsidiary of Gordian International LLC located in Gilbert, Arizona, a semiconductor packaging and international engineering management company with a global client base. He is a highly influential in advanced IC packaging technology circles in areas including Wafer Level Packaging, high density PWB technologies, Fan-In & Fan-Out WLP technologies, flip chip and Cu pillar bumping and assembly and heterogeneous integration. He has managed global engineering organizations at CTO levels for 20+ years. He specializes and practices Open Innovation strategies, successfully drives technology development & deployment into overseas OSAT factories for his clients. Ted has 25+ years of industry experience and has published more than 150 conference papers and journal publications and has 12 patents issued in a wide array of advanced packaging areas. He also has broad interests and involvement in leading edge packaging solutions for Artificial Intelligence, Medical Electronics, Internet of Things, MEMS / Sensors and Technology Investment Strategies. Ted graduated with a HBSc. degree in Organic Chemistry from Laurentian University, Sudbury Ontario and a Master’s degree in Applied Polymer Chemistry from the University of Ottawa, Ottawa, Ontario Canada.





Wafer-Level Packaging

Saurabh Nilkanth Athavale

Chair: Saurabh Nilkanth Athavale, Ph. D., Western Digital

Saurabh holds a Master’s degree in mechanical engineering and Doctoral degree in Industrial and Systems Science from State University of New York (Binghamton University). He has over 10 years of experience in the semiconductor industry. Prior to joining Western Digital he was responsible for advanced wafer level packaging and board level reliability activities.




Tom Strothmann

Co-Chair: Tom Strothmann, Besi North America, Inc.

Tom Strothmann is the former Director for Advanced Packaging Next-Generation Products at Kulicke & Soffa Industries, Inc. Prior to joining K&S, Tom managed Wafer Level Products Business Development for STATS ChipPAC, including Fan-In and Fan-Out WLP. Before STATS ChipPAC, Tom was Vice President of Business Development at FlipChip International and responsible for the formation of FlipChip Millennium Shanghai Co. At FlipChip Technologies, Tom successfully managed the transfer of bumping technology and the startup of bump lines for all major OSATS. Tom has 20 years' experience in technology development for wafer bumping and related Advanced Packaging technologies and extensive experience in front end semiconductor manufacturing.




Jacinta Aman Lim

Jacinta Aman Lim, Nepes

Jacinta Aman Lim has over 20 years of experience in Wafer Level Packaging (Fan-In and Fan-Out), OSAT selection and management, product and package design, product reliability and business development. Jacinta is currently the Technical Director for Business Development at Nepes Corporation. Prior to joining Nepes, Jacinta was the Deputy Director of Business Development for Wafer Level Packaging at STATS ChipPAC. She specializes in advanced Fan-Out packaging (multi die, multi RDL, FOWLP- SiP). She has also worked at Skyworks Solutions, Amkor, Intel and FlipChip International. Jacinta graduated from Arizona State University with her Master of Science in Materials Science Engineering and Bachelor of Science in Electrical Engineering. She also holds a Master in Business Administration with emphasis on Technology Management and a degree in Pianoforte from the Royal Academy of Music in London. In her free time, Jacinta is an avid Bikram Yoga practitioner, enjoys gardening, reading and traveling.




Tanja Braun

Tanja Braun, Ph.D, Fraunhofer IZM

Tanja Braun studied mechanical engineering at Technical University of Berlin with a focus on polymers and micro systems and joined Fraunhofer IZM in 1999. Since 2000 she is working with the group Assembly & Encapsulation Technologies and since 2016 she is head of this group. In 2013 she received her Dr. degree from the Technical University of Berlin for the work focusing on humidity diffusion through particle-filled epoxy resins. Her field of research is process development of assembly and encapsulation processes, the qualification of these processes using both non-destructive and destructive tools and advanced polymer analysis. Recent research is focused on wafer and panel level packaging technologies and Tanja Braun is leading the Fan-out Panel Level Packaging Consortium at Fraunhofer IZM Berlin.




Burt Carpenter

Burt Carpenter, NXP Semiconductors

Burt Carpenter is a Sr. Principal Engineer at NXP Semiconductors in Austin, TX, where he drives package strategy on various automotive package platforms. During the past 24 years, Burt has held various positions in BGA process development, design, modeling, and package integration as the company transitioned ownership from Motorola to Freescale to NXP. Prior to that he worked in PCB process development at IBM. Burt holds a BS and MS in Materials Engineering from Rensselaer Polytechnic Institute.




Takenori Fujiwara

Takenori Fujiwara, Ph.D., Toray Industries, Inc.

Dr. Fujiwara is currently a Research Associate and has more than 20 years of experience in the electronics industry primarily centered on materials R&D for use in microelectronics, optics and display technologies, spanning a variety of senior technology. He is familiar with high heat resistance polymers (polyimides and spin on glass (SOG) and other various materials. Additional expertise with development of incubation technologies in consortium includes TPEC (Tsukuba Power Electronics Constellations) in Japan on a 500oC heat resistance photoresist for high heat ion implantation and a stress buffer coating of polyimide for SiC power semiconductors and the IME (Institute of Microelectronics) in Singapore. He has collaborated with IME over 3 years though consortiums of FOWLP, 3DIC, Intelligent power module and Antenna in Package including materials for RDL dielectrics, temporary bonding de-bonding, non-conductive films and thermal interfaces. He has published numerous advanced semiconductor material papers and holds various patents for the materials and ancillary development work. He holds a Ph.D in material engineering from Nagoya University (2008).




Timo Henttonen

Timo Henttonen, Microsoft

Timo Henttonen is a director of IC packaging at Microsoft in Sunnyvale (CA), where he manages IC package technologies for a variety of end system products. He joined Microsoft 2014 after twenty-year career at Nokia, where he held various global IC packaging operations and technology management roles. In addition to his work in Packaging, he has also managed development of PCB and Flexible Printed Circuits for mobile applications. Mr. Henttonen has made significant contributions to the development of various IC packaging platforms (1st BGAs for mobile, high reliability lead-free metallurgies, 1st PoP, high reliability WLCSP with large die) currently being used in the wireless industry. Mr. Henttonen is a member of IEEE Electronics Packaging Society, has been an invited speaker to ECTC as well as the SEMI European 3D TSV Summit, and holds a master's degree in Electrical Engineering from Tampere University of Technology (Finland).




Jan Vardaman

Jan Vardaman, TechSearch International, Inc.

Jan Vardaman is the editor of Surface Mount Technology: Recent Japanese Developments, co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbun), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center study team involved in investigating electronics manufacturing in Asia and on the US mission to study manufacturing in China. She is a member of IEEE CPMT, IMAPS, SMTA, and SEMI. She was elected to two terms on the IEEE CPMT Board of Governors. She received her BA in Economics and Business from Mercer University in Macon, Georgia in 1979 and her MA in Economics from the University of Texas at Austin in 1981.





Advanced Manufacturing & Test

Garrett Oakes

Chair: Garrett Oakes, EV Group

Garrett Oakes is the Director of Technology for EV Group North America in Tempe, Arizona. Since joining EV Group in 2006, he has held positions in Strategic Sales and Applications Engineering. In his current role, he is responsible for the day-to-day operations of the applications lab and managing the efforts of the engineering organization. Prior to EVG, he spent eleven years as a photolithography process and development engineer for IBM and Hitachi in their storage technology divisions. Garrett holds a degree in Chemical Engineering from the University of California at Davis. He also holds several U.S. patents on the subject of temporary bond and debond for back end wafer processing.




Keith Best

Keith Best, Onto Innovation

For more than 30 years, Keith Best has held a range of semiconductor processing and applications positions for both device manufacturing and capital equipment companies, of which 13 years were with ASML. He is currently the Director of Applications Engineering at Onto Innovation (formerly Rudolph Technologies) where he supports the JetStep® advanced packaging lithography stepper. Keith holds a B.Sc. Honors Degree in Materials Science from the University of Greenwich, UK. He has numerous publications and holds 17 US patents in the areas of photolithography and process integration.




Habib Hichri

Habib Hichri, Ph.D.

Habib spent about 12 years with IBM Semiconductors Research and Development Center in East Fishkill, NY where he worked as lead process integration engineer for microprocessor (IBM), games and communications chips. He later was promoted to management position within IBM on process development in lithography and Dry Reactive Ion Etch in the front end of line area for microprocessor fabrication. Habib holds over 35 U.S. patents and authored over 30 publications and presentations. Habib received Master and PhD degrees in Chemical Engineering from the Claude Bernard University at Lyon, France and an MBA degree from the State University of New York at Buffalo.




Scott Jewler

Scott Jewler, SVXR, Inc.

Scott Jewler is a semiconductor industry veteran with extensive experience in the outsourced semiconductor assembly and test industry. Scott currently serves as Chief Operating Officer and Board Director for SVXR, a sub-surface inspection equipment design and manufacturing company which he co-founded in 2012. Scott was Sr. Director of Global Operations for Globalfoundries from 2014 to 2018. Prior to that, Scott held senior executive positions at three of the four largest OSAT's in the world by revenue. From 2009 to 2012, Scott served as Chief Engineering and Sales officer for Powertech Technology where he was based in Hsinchu, Taiwan. While at PTI. Scott led the development of advanced TSV and 3DIC interconnect technologies. Prior to PTI, Scott served as Chief Strategy Officer for STATS ChipPAC where he was responsible for corporate strategy, product management, and global sales. During his tenure, STTS was the faster growing major OSAT in the industry. Prior to STTS, Scott was President of Amkor Technology Taiwan where he was responsible for two manufacturing sites with over 3000 employees. During his tenure at Amkor, Scott led the introduction of QFN packaging technology. Scott has a B.S. degree in Mechanical Engineering from Clemson University and holds 7 US patents in IC packaging.








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Organized by: SMTA and ChipScale Review



Supported by:
IEEE Electronic Packaging Society

Supporting Media:
MEPTEC