IWLPC Technical Committee

If you are interested in being part of the technical committee, contact IWLPC, iwlpc@iwlpc.com or +1-952-920-7682.

3D Integration

John Lannon

Co-Chair: John Lannon, Ph.D., Micross Advanced Interconnect Technology

Dr. John Lannon is the General Manager of Micross Advanced Interconnect Technology, a business unit of Micross focused on wafer-level advanced packaging, interconnect, and device integration technologies. Since receiving his Ph.D. degree in Physics from WVU in 1996, he has worked on the development of thin film materials and advanced packaging processes (e.g. high density interconnects, TSV integration, and wafer-level vacuum packaging) for next generation microsystems in sensor and scene projector applications.

Laurette Nacamulli

Laurette Nacamulli, The Dow Chemical Company

Laurette Nacamulli is Strategic Account Manager for Dow Chemical Electronic Materials – Advanced Packaging Technologies where she is responsible for promoting Dow's packaging portfolio consisting of metallization and polymers. Laurette holds a BS in Chemistry and MS in electrochemistry both from Tel Aviv University, Israel. Previously, Laurette was a senior process engineer at Intel and held positions at Igen and Technicon developing electrochemical methods for diagnostics. She has authored papers and has a patent on electrochemiluminescence.

Herb Reiter, eda 2 asic Consulting, Inc.

After more than 20 years in technical and business roles at ASIC vendors and EDA software companies, Herb founded eda2asic Consulting, Inc. in 2002. Initially he focused on business development work to introduce products and services developed by mostly smaller EDA firms to major ASIC vendors. He introduced tools and IP for simplifying and accelerating SoC design efforts for integrating single die solutions into IC packages. Herb earned MSEE and MBA degrees in Austria/Europe, an MBA at San Jose State University and has attended 40+ Continuing Education Classes at Stanford University.

Kim Yess

Kim Yess, Brewer Science

Kim Yess, Technology Director for Wafer Level Packaging Materials business, has been employed with Brewer Science since 1989. She holds several granted patents in the area of anti-reflective chemicals developed specifically for the integrated circuits industry, etch protective materials used for applications within the MEMS arena and polymeric adhesives and processes for wafer thinning packaging applications. In her current role she is responsible for identifying development opportunities of new products and applications and manages the operations aspects of the developmental activities within the WLPM business. Kim resides on several technical committees for conference organizations including ECTC and IMAPS. Kim Yess holds an MBA from Webster University and a B.A. (Biology/Chemistry) from Central Missouri State University.

Wafer-Level Packaging

Saurabh Nilkanth Athavale

Chair: Saurabh Nilkanth Athavale, Ph. D., Western Digital

Saurabh holds a Master’s degree in mechanical engineering and Doctoral degree in Industrial and Systems Science from State University of New York (Binghamton University). He has over 10 years of experience in the semiconductor industry. Prior to joining Western Digital he was responsible for advanced wafer level packaging and board level reliability activities.

Tom Strothmann

Co-Chair: Tom Strothmann, Besi North America, Inc.

Tom Strothmann is the former Director for Advanced Packaging Next-Generation Products at Kulicke & Soffa Industries, Inc. Prior to joining K&S, Tom managed Wafer Level Products Business Development for STATS ChipPAC, including Fan-In and Fan-Out WLP. Before STATS ChipPAC, Tom was Vice President of Business Development at FlipChip International and responsible for the formation of FlipChip Millennium Shanghai Co. At FlipChip Technologies, Tom successfully managed the transfer of bumping technology and the startup of bump lines for all major OSATS. Tom has 20 years' experience in technology development for wafer bumping and related Advanced Packaging technologies and extensive experience in front end semiconductor manufacturing.

Tanja Braun

Tanja Braun, Ph.D, Fraunhofer IZM

Tanja Braun studied mechanical engineering at Technical University of Berlin with a focus on polymers and micro systems and joined Fraunhofer IZM in 1999. Since 2000 she is working with the group Assembly & Encapsulation Technologies and since 2016 she is head of this group. In 2013 she received her Dr. degree from the Technical University of Berlin for the work focusing on humidity diffusion through particle-filled epoxy resins. Her field of research is process development of assembly and encapsulation processes, the qualification of these processes using both non-destructive and destructive tools and advanced polymer analysis. Recent research is focused on wafer and panel level packaging technologies and Tanja Braun is leading the Fan-out Panel Level Packaging Consortium at Fraunhofer IZM Berlin.

Bora Baloglu

Bora Baloglu, Ph.D., Amkor Technology Europe Portugal

Bora joined Amkor in 2011 and has supported computational analyses and package and board level reliability for a variety of semiconductor package types. He is currently responsible for managing Research and Development activities for Amkor's Advanced Wafer Level Fan-Out products. Bora serves on various technical conference committees and holds 12 patents, with 20 additional patents pending in the semiconductor packaging field. Prior to joining Amkor, Bora was a research assistant at Lehigh University. He holds master's and Ph.D. degrees in mechanical engineering from Lehigh University in Bethlehem, PA.

Burt Carpenter

Burt Carpenter, NXP Semiconductors

Burt Carpenter is a Sr. Principal Engineer at NXP Semiconductors in Austin, TX, where he drives package strategy on various automotive package platforms. During the past 24 years, Burt has held various positions in BGA process development, design, modeling, and package integration as the company transitioned ownership from Motorola to Freescale to NXP. Prior to that he worked in PCB process development at IBM. Burt holds a BS and MS in Materials Engineering from Rensselaer Polytechnic Institute.

Jacinta Aman Lim, StatsChip Pac

Timo Henttonen

Timo Henttonen, Microsoft

Timo Henttonen is a director of IC packaging at Microsoft in Sunnyvale (CA), where he manages IC package technologies for a variety of end system products. He joined Microsoft 2014 after twenty-year career at Nokia, where he held various global IC packaging operations and technology management roles. In addition to his work in Packaging, he has also managed development of PCB and Flexible Printed Circuits for mobile applications. Mr. Henttonen has made significant contributions to the development of various IC packaging platforms (1st BGAs for mobile, high reliability lead-free metallurgies, 1st PoP, high reliability WLCSP with large die) currently being used in the wireless industry. Mr. Henttonen is a member of IEEE Electronics Packaging Society, has been an invited speaker to ECTC as well as the SEMI European 3D TSV Summit, and holds a master's degree in Electrical Engineering from Tampere University of Technology (Finland).

Jan Vardaman

Jan Vardaman, TechSearch International, Inc.

Jan Vardaman is the editor of Surface Mount Technology: Recent Japanese Developments, co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbun), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center study team involved in investigating electronics manufacturing in Asia and on the US mission to study manufacturing in China. She is a member of IEEE CPMT, IMAPS, SMTA, and SEMI. She was elected to two terms on the IEEE CPMT Board of Governors. She received her BA in Economics and Business from Mercer University in Macon, Georgia in 1979 and her MA in Economics from the University of Texas at Austin in 1981.

Advanced Manufacturing & Test

Garrett Oakes

Chair: Garrett Oakes, EV Group

Garrett Oakes is the Director of Technology for EV Group North America in Tempe, Arizona. Since joining EV Group in 2006, he has held positions in Strategic Sales and Applications Engineering. In his current role, he is responsible for the day-to-day operations of the applications lab and managing the efforts of the engineering organization. Prior to EVG, he spent eleven years as a photolithography process and development engineer for IBM and Hitachi in their storage technology divisions. Garrett holds a degree in Chemical Engineering from the University of California at Davis. He also holds several U.S. patents on the subject of temporary bond and debond for back end wafer processing.

Shekar Krishnaswamy

Co-Chair: Shekar Krishnaswamy, Applied Materials

Shekar has over 27 years of experience in all aspects of semiconductor manufacturing including wafer fab manufacturing, assembly and test. He started his career in IBM-Fishkill working in the advanced packaging segment focused on manufacturing multi-layer ceramic packages. His specific areas of expertise include traditional Industrial Engineering methods as well as systems related methodologies such as modeling, scheduling, dispatching and factory automation. Shekar has held senior technical and management positions at IBM, Motorola and AMD including management of corporate Operations Research departments supporting factory and service groups. Shekar has a Bachelor's degree in Mechanical Engineering and a Master's degree in Industrial Engineering and Operations Research.

Ira Feldman

Ira Feldman, Feldman Engineering Corp.

Ira Feldman manages and develops unique high technology solutions and business strategies as a principal consultant at Feldman Engineering Corp. FEC supports clients with technical marketing and product generation processes. His expertise includes high volume manufacturing of complex technology products in the consumer electronics, semiconductor test, and computer test industries covering a wide size range of products and technologies from microfabricated 3D fully-assembled micro-machines to Automated Test Equipment (ATE) and mini-computers. Mr. Feldman has worked at both startups (NanoNexus and Microfabrica) and global companies (Hewlett-Packard and Agilent Technologies). He is the General Chair of TestConX formerly the Burn-in & Test Strategies (BiTS) Workshop. And he earned BS and Master of Engineering degrees from Harvey Mudd College.

Dale Gee

Dale Gee

Dale holds a Bachelor's Degree in Chemical Engineering from UC Berkeley, and an MBA from Santa Clara University. Dale began his career at Motorola Semiconductors in 1982 as a Device Engineer and throughout the 1980s, 1990s, and 2000s held various engineering, management, and executive positions with integrated circuit, sensor, and MEMS companies including Hewlett-Packard, Foxboro/ICT, Nayna Networks, Symyx Technologies, Visyx Technologies, TRW, GE Sensing, and Amphenol-NovaSensor. Dale is currently Product Engineering Manager at TDK/Invensense.

Habib Hichri

Habib Hichri, Ph.D., SÜSS MicroTec Inc.

Habib Hichri joined SUSS MicroTec on October 2013 as Engineering Applications Director in Corona CA, USA. Before joining SUSS MicroTec, Habib spend about 12 years with IBM Semiconductors Research and Development Center in East Fishkil, NY where he worked as lead process integration engineer for microprocessor (IBM), games and communications chips. He later was promoted to management position within IBM on process development in lithography and Dry Reactive Ion Etch in the front end of line area for microprocessor fabrication. Habib holds over 35 U.S. patents and authored over 30 publications and presentations. Habib received Master and PhD degrees in Chemical Engineering from the Claude Bernard University at Lyon, France and an MBA degree from the State University of New York at Buffalo.

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Organized by: SMTA and ChipScale Review

Supported by:
IEEE Electronic Packaging Society

Supporting Media:
MEPTEC Open Sky Communications