Advanced Packaging in the New Connected World
October 22 - 24, 2019
DoubleTree by Hilton San Jose
San Jose, California, USA

Professional Development Courses (PDCs)

Thursday, October 24, 2019

The IWLPC courses are application-oriented and structured to combine field experience with scientific research to solve everyday problems.

  • PDC1 - Evolution from Basic to Advanced Fan Out
  • PDC2 - Polymers in Wafer Level Packaging
  • PDC3 - Modeling Failure Modes for Chip Package Interactions and Package Level Reliability
  • PDC4 - Fan-Out Wafer/Panel-Level Packaging and Heterogenous Integrations

  • Morning Courses


    Evolution from Basic to Advanced Fan Out

    John Hunt John Hunt, ASE (US) Inc.
    October 24, 2019
    8:30am–12:00pm | Donner Pass Ballroom

    Fan Out technology has evolved as an alternative package to meet the need for miniaturization of electronics, while also providing improved electrical interconnectivity. Until around 2016, Fan Out was considered primarily a solution for low density packaging requirements. We will review how the integration of wafer level processing technologies; substrate evolution and Flip Chip packaging structures have come together into recent advances in both low density and high-density Fan Out packaging. These packages are for automotive, IoT, advanced mobile and server applications. They can have higher levels of integration and sophistication than has ever been possible in the past. A brief overview of the concept of Fan Out packaging and history of its evolution, as well as Fan Out developments to meet both low- and high-end applications using both Wafer Level and Panel Level processing will be included in this course.

    Who Should Attend?
    Anyone who is involved with advanced packaging who wants to understand Fan Out structures, processes, capabilities and limitations. Including Semiconductor Engineers, Packaging Engineers, Application Engineers, and Purchasing individuals who may require knowledge of Fan Out in the course of their duties.


    Polymers in Wafer Level Packaging

    Jeffrey Gotro, Ph.D. Jeffrey Gotro, Ph.D., InnoCentrix, LLC
    October 24, 2019
    8:30am-12:00pm | Siskiyou Ballroom

    The course will provide an overview of polymers and the important structure-property-process-performance relationships for polymers used in wafer level packaging. The main learning objectives will be: 1) understand the types of polymers used in wafer level packages, including underfills (pre-applied and wafer applied), mold compounds, and substrate materials 2) gain insights on how polymers are used in Fan Out Wafer Level Packaging, specifically mold compounds and polymer redistribution layers (RDL) 3) learn the key polymer and processes challenges in Fan Out Wafer Level Packaging..

    Who Should Attend?
    Packaging engineers involved in the development, production, and reliability testing of electronic packages would benefit. Those interested in gaining a basic understanding of the role of polymers and polymer-based materials used in electronic packaging will also find this PDC valuable.

    Afternoon Courses


    Modeling Failure Modes for Chip Package Interactions and Package Level Reliability

    Gil Sharon Gilad Sharon, Ph.D., ANSYS
    October 24, 2019
    1:30pm-5:00pm | Donner Pass Ballroom

    This course will cover prediction methodologies for flip chip die and package level reliability. The mechanical process for several failure modes will be discussed with examples of die cracking, bump fatigue, white bump, package warpage, board level reliability and microvia failures. Modeling methodologies for each of the failure modes will be shown. Possible mitigation strategies and options at the package level will be explored. The physical and mechanical processes of attaining reliability are an integral part of this course. Participants are expected to have a basic knowledge of BGA, QFN and Package-on-Package structures. Participants should also be familiar with finite element modeling and analysis methods.

    Who Should Attend?
    This course is directed towards the fabless semiconductor manufacturing segment. Participants should be involved in design, manufacturing or purchasing of flip chip packaging services. This course will be especially helpful to device manufacturers and designers.


    Fan-Out Wafer/Panel-Level Packaging and Heterogenous Integrations

    Dr. John H. Lau John Lau, Ph.D., Unimicron Technology Corporation
    October 24, 2019
    1:30pm-5:00pm | Siskiyou Ballroom

    Fan-out wafer-level packaging (FOWLP) has been getting lots of tractions since TSMC used their InFO to package the application processor for the iPhone 7. In this lecture, the following topics will be presented and discussed. Emphasis is placed on the fundamentals and latest developments of these areas in the past three years. Their future trends will also be explored. The lecture materials are mainly from the latest book (Fan-Out Wafer-Level Packaging, Springer, 2018) authored by the lecturer and every attendee will receive > 150 pages of lecture handouts. Heterogeneous integration uses packaging technology to integrate dissimilar chips, photonic devices, and/or components (side-by-side and/or stack) with different materials and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem. System-in-package (SiP) is very similar to heterogeneous integration, except heterogeneous integration is for finer pitches, more inputs/outputs (I/Os), higher density, and higher performance. For the next few years, we will see more implementations of a higher level of heterogeneous integration, whether it is for time-to-market, performance, form factor, power consumption or cost. In this lecture, the introduction, recent advances, and trends in heterogeneous integrations will be presented. The lecture materials are mainly from the latest book (Heterogeneous Integrations, Springer, April 2019) authored by the lecturer and every attendee will receive >150 pages of lecture handouts.

    Who Should Attend
    If you (students, engineers, and managers) are involved with any aspect of the semiconductor packaging and electronics assemblies, you should attend this course. It is equally suited for R&D professionals and scientists. All the materials are based on the papers and books published in the past 3 years and each participant will receive more than 200 pages of the lecture notes.

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    Organized by: SMTA and ChipScale Review

    Supported by:
    IEEE Electronic Packaging Society

    Supporting Media:
    MEPTEC Open Sky Communications