Bridging the Boundaries: Wafer, Panel and Beyond
October 13 - 15, 2020
DoubleTree by Hilton San Jose
San Jose, California, USA

Call for Papers

International Wafer-Level Packaging Conference

The SMTA and Chip Scale Review are pleased to announce plans for the 17th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition. This premier industry event explores leading-edge design, material, and process technologies being applied to Wafer-Level Packaging applications. There will be special emphasis on the numerous device and end product applications (RF/wireless, sensors, mixed technology, optoelectronics) that demand wafer level packaging solutions for integration, cost, and performance requirements.

The IWLPC Technical Committee would like to invite you to submit an abstract for this program.
Still Accepting Abstracts

IMPORTANT: Please be sure to obtain approval to both write and present your paper prior to submitting an abstract. When a paper is accepted by the Technical Committee, it is our expectation that you have budget approval for travel costs and conference registration which is required for speakers.

The conference includes three tracks with two days of technical paper presentations covering: Wafer-Level, 2.5D & 3D packaging, and Advanced Manufacturing & Test. Also, the conference offers professional development courses (PDCs).

Wafer-Level Packaging:
Wafer Level Chip Scale Packaging (WLCSP), Flip-chip, Fan-Out and Redistribution, Wafer and Device Cleaning, MEMS, sensors, Nanotechnology, Quality, Reliability, and COO.

3D Package Integration:
3D WLP, Thru Silicon Vias (TSV), Thru Glass Vias (TGV), Silicon Interposers, Stacking Processes (W2W, D2W, D2D), IC Packaging Substrates, TSV Integration methods (FEOL vs BEOL), Package-on-Package (PoP), embedded die and passives, and EMI shielding methods.

Advanced Wafer-level Manufacturing and Test
Advances in wafer-level manufacturing processes, equipment and materials including: novel process or material technologies, improved equipment throughput and productivity, control methodologies (SPC, APC, FDC), factory output & cycle time improvements, advanced automation technologies, warped wafer handling, wafer level test methods, wafer level vs. singulated unit test for WLP, and TSV test methods.

If you would like to present at this conference, please submit a 200-300 word abstract. Please include a title, author name, and contact information with your abstract.
Note that technical papers are required and will be due Friday, August 28th, 2020.

For more information on the conference, exhibition, or sponsorship opportunities, please contact or +1-952-920-7682.

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Organized by: SMTA and ChipScale Review

Supported by:
IEEE Electronic Packaging Society

Supporting Media: