Bridging the Boundaries: Wafer, Panel and Beyond
October 13 - 15, 2020
DoubleTree by Hilton San Jose
San Jose, California, USA


The IWLPC tutorials are application-oriented and structured to combine field experience with scientific research to solve everyday problems. They are offered on Thursday, October 20.

  • WS1 - Introduction to Fan-Out Wafer Level Packaging
  • WS2 - Wafer Level Packaging for the Functional Integration of MEMS and ICs
  • WS3 - Choosing the Right IC Packaging
  • WS4 - Recent Advances and New Trends in Semiconductor Packaging

  • WS1

    Introduction to Fan-Out Wafer Level Packaging

    Beth Keser, Ph.D., Qualcomm
    Thursday, October 20, 2016 | 8:30am-12:00pm

    Fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 8 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wirebond and bump interconnections, substrates, leadframes, and the traditional flip chip or wirebond chip attach and underfill assembly technologies across multiple applications. This course will cover the advantages of FO-WLP, potential application spaces, package structures available in the industry, process flows, material challenges, design rule roadmap, reliability, and benchmarking. This course has been updated with over 10% new material compared to the first time it was offered last year at IWLPC.

    1. Current Challenges in Packaging
    2. Definitions and Advantages
    3. Applications
    4. Package Structures including Advanced FO technologies
    5. Process
    6. Material Challenges
    7. Equipment Challenges
    8. Design Rules
    9. Technology Roadmap
    10. Reliability
    11. Benchmarking

    Who Should Attend
    Engineers and managers responsible for advanced packaging development, package characterization, package quality, package reliability and package design should attend this course. Both newcomers and experienced practitioners are welcome.

    Instructor Biography
    Beth Keser Beth Keser has over 17 years experience in the semiconductor industry. Beth received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. in Materials Science and Engineering at the University of Illinois at Urbana-Champaign. Beth’s development of materials and packaging technologies for the semiconductor industry has resulted in 8 patents, over 10 patents pending, and over 40 publications in this area. Currently, Beth is the Fan-Out Wafer Level Packaging Technology Manager at Qualcomm, San Diego. Before joining Qualcomm in 2009, Beth Keser was instrumental in developing 2 packaging technologies during her career at Motorola and Freescale Semiconductor. Beth led the Wafer-Level Chip Scale packaging team at Motorola, which included directing the activities of process engineering, package characterization, package reliability, and mechanical modeling. In addition, Beth Keser was the lead technologist and manager of the Redistributed Chip Packaging Technology (RCP). Beth led the team that developed this technology for 6 years. Beth developed several process and material solutions for this new technology.


    Wafer Level Packaging for the Functional Integration of MEMS and ICs

    Chip Spangler, Ph.D. Aspen Microsystems LLC
    Thursday, October 20, 2016 | 8:30am–12:00pm

    The development of wafer-level packaging (WLP) has been a major driving force for the size and cost reduction for both integrated circuits as well as MEMS, microsystems, micro-optical and microfluidic products. Collectively referred to as MEMS, these devices require highly specialized packages that protect the fragile microstructures and still allow the desired signals, both electric and non-electric, to pass through the package to the die. The challenges and costs associated with MEMS packaging has, since the 1970’s, driven the development of wafer-level packaging and associated technologies such as silicon and glass interposers, through wafer vias, wafer bonding and die stacking. Cost and size demands have since lead to the widespread adaptation of these MEMS-based WLP technologies by the integrated circuit package community. More recently the demand for multi-sensor products, greater levels of sensor intelligence and the connectivity requirements of IoT applications has driven the complex integration of MEMS and ICs through the use of WLP technologies.


  • MEMS and Microsystem products and applications
  • Requirements for MEMS packages
  • MEMS WLP technologies
  • WLP technologies to integrate MEMS and ICs
  • Future trends and applications for MEMS WLP

    Who Should Attend?
    Given the strong interaction of MEMS devices with their the package and associated electronics, this course will be highly beneficial to all students, engineers, product designers, scientists and managers who are working in the field of MEMS and microsystems, micro optics and microfluidics. With a focus on practical implementation, those designing new microsystem products will benefit from the breadth and depth of the technologies being presented. This course will also be of particular value for those who are transition existing MEMS and microsystem products from conventional packages to smaller wafer-level packages.

    Leland Chip Spangler, Ph.D.

    Instructor Biography
    Dr. Spangler received his Ph.D. in electrical engineering from The University of Michigan in 1988 and is currently the President of Aspen Microsystems, LLC a microsystems product development and intellectual property company with specialization in semiconductor devices, packaging and assembly.

    Chip was previously the President and CTO of Aspen Technologies a semiconductor package design and assembly subcontracting company that provided services for customers in medical, industrial, telecom and mil-aero markets. Among these products were ultra high-resolution displays, several DNA analysis products, implantable devices for neuromodulation, and MEMS switch arrays for telecom applications. Prior to this, Chip was employed at Ford Microelectronics where he had responsibility for a number of microelectronic programs including analog IC design, pressure sensors, micro-machined fuel injectors, as well as airbag and chassis accelerometers. His work lead directly to the production of the world's first wafer-level packaged, plastic surface-mount airbag accelerometer.

    Dr. Spangler is the author of over 30 technical publications and 9 patents. He is currently an editor for IEEE Journal of Microelectromechanical Systems (JMEMS) and he serves on the board of directors several organizations. He has also been active in organizing a number of technical conferences including the biannual Transducers Conference as well as the Hilton Head Solid State Sensor Workshop.



    Choosing the Right IC Packaging

    Chet Palesko, SavanSys Solutions LLC and Jan Vardaman, TechSearch International, Inc.
    Thursday, October 20, 2016 | 1:30pm-5:00pm

    In this course, we will analyze the performance and size characteristics of traditional (lead frame options, wire bond PBGA, flip chip PBGA) and advanced packaging (wafer level packaging, fan-out WLP options, embedded die, 2.5D/interposer-based packaging, 3D packaging with through silicon vias). For each packaging technology, this course also provides a detailed cost analysis including the manufacturing process flow to fabricate and assemble the package and the dominant technology cost drivers.

    This course will also examine how OEMs and suppliers can collaborate to develop a model which optimizes product manufacturing cost for IC packages. This modeling approach has been successfully used by a number of major OEMs and suppliers in North America, Europe, and Asia to match design technology choices with supplier competencies. Yields are improved and cost reduction is achieved across the entire supply chain.


  • Packaging Trade off Overview
  • Traditional Packaging Technologies
  • Advanced Packaging Technologies
  • Packaging Trends
  • Practical Cost Modeling Considerations

    Who Should Attend?
    This course is designed for anyone involved in packaging technology and selection. This includes system designers, package designers, procurement personnel, design managers, and product managers. This course is beneficial for those who want to better understand the actual costs and yields associated with different packaging technologies, as well as for those who require a more complete understanding of their supply chain.

    Instructor Biographies
    Chet Palesko Chet Palesko is currently President of SavanSys Solutions LLC. SavanSys Solutions LLC ( provides cost modeling services and software to suppliers and OEMs. Mr. Palesko has developed dozens of electronic manufacturing cost models for major telecommunication, computer, and aerospace companies. Previously, he spent 12 years at Mentor Graphics in a variety of roles including general management, engineering, marketing, and sales. In 1995, Mr. Palesko co-founded Savantage Inc., where he led the global development and sales of SavanSys.

    Jan Vardaman Jan Vardaman is the editor of Surface Mount Technology: Recent Japanese Developments, co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbun), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center study team involved in investigating electronics manufacturing in Asia and on the US mission to study manufacturing in China. She is a member of IEEE CPMT, IMAPS, SMTA, and SEMI. She was elected to two terms on the IEEE CPMT Board of Governors. She received her BA in Economics and Business from Mercer University in Macon, Georgia in 1979 and her MA in Economics from the University of Texas at Austin in 1981.


    Recent Advances and New Trends in Semiconductor Packaging

    John H. Lau, Ph.D., ASM Pacific Technology
    Thursday, October 20, 2016 | 1:30pm-5:00pm

    Recent advances in, e.g., fan-out wafer/panel level packaging (TSMC’s InFO-WLP and IZM’s FO-PLP), 3D IC packaging (TSMC’s InFO_PoP vs. Samsung’s ePoP), through-silicon vias (TSVs), microbumps, 3D IC integration (Hynix/Samsung’s HBM for AMD/NVIDIA’s GPU vs. Micron’s HMC for Intel’s Knights Landing CPU), 2.5D IC Integration (TSV-less interconnects and interposers), embedded 3D hybrid integration (of VCSEL, driver, serializer, polymer waveguide, etc.), 3D CIS/IC integration, 3D MEMS/IC integration, thin-wafer Handling, thermal management, semiconductor and packaging for IoTs are examined, and their new trends will be discussed in this lecture. The patents impacting the semiconductor packaging the most (so far) will be mentioned first and the patent issues of fan-out wafer/panel-level will be discussed and some recommendations will be made.

    Course Outline

  • Introduction
  • Patents Impacting the Semiconductor Packaging
  • Fan-Out Wafer/Panel-Level Packaging
  • TSV Technology
  • Micro Bumping, Assembly, and Reliability
  • 3D IC Integration
  • 2.5D IC Integration
  • Thermal Management of 2.5D.3D IC Integration
  • Embedded 3D Hybrid Integration

    Who Should Attend?
    If you (students, engineers, and managers) are involved with any aspect of the electronics, and optoelectronic industry, you should attend this course. It is equally suited for R&D professionals and scientists. Each participant will received more than 200 pages of handout materials from others and the lecturer’s books, Advanced MEMS Packaging (McGraw-Hill, 2010), Reliability of RoHS compliant 2D and 3D IC Interconnects (McGraw-Hill, 2011), TSV for 3D Integration, (McGraw-Hill, 2013), and 3D IC Integration and Packaging (McGraw-Hill, 2015).

    Instructor Biography
    Dr. John H. Lau Dr. John H. Lau has been a Sr. Technical Advisor of ASM since July 2014. Prior to that, he was an ITRI Fellow of Industrial Technology Research Institute (Taiwan) for 4.5 years, a visiting professor at HKUST for 1 year, the Director of MMC Laboratory with IME Singapore for 2 years and a Senior Scientist/MTS at Hewlett-Packard/Agilent in California, US for more than 25 years. With more than 38 years of R&D and manufacturing experience, he has published more than 441 peer-reviewed papers, 30 issued and pending patents, and 18 textbooks. John received many awards and is an elected ASME Fellow and has been an IEEE Fellow since 1994.

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    Organized by: SMTA and ChipScale Review

    Supported by:
    IEEE Electronic Packaging Society

    Supporting Media: