Bridging the Boundaries: Wafer, Panel and Beyond
October 13 - 15, 2020
DoubleTree by Hilton San Jose
San Jose, California, USA

Reflections on IWLPC 2016

By Louis Burgyan, LTEC Corporation

The 13th International Wafer-Level Packaging Conference (IWLPC) and Exhibition, held in Silicon Valley on October 18-20, offered an excellent insight into current issues and future challenges in advanced packaging technologies. An impressive array of 48 presentations, five interactive presentations (poster sessions), and four workshops covered a wide array of topics with focus on various aspects of fan-out wafer-level packaging (FOWLP), 3D packaging and manufacturing, and microelectromechanical systems (MEMS). Overall, attendance was higher than what I've seen in past years, and the expo hall was sold out completely. Table-top exhibitors, who couldn't get space inside the main exhibition hall, lined up their display items along the walkways in front of the main exhibit area. Quite fittingly, the main theme of the conference was "Bridging the Interconnect Gap," thus highlighting one of the major challenges our industry is facing as "big data" seeps into our daily lives in multiple forms at the workplace, home, and in between.

Cognitive computing, mobile communication, connected vehicles, cloud-connected Internet of Things (IoT) devices—all require fast processing locally and through the cloud with access to massive amounts of data, regardless of its location. The brick and mortar of the underlying hardware environment is advanced packaging technology that needs to facilitate interconnectivity among often heterogeneous systems within a package. Processors, memories, and logic devices need to interact at multi-gigabit per second data rates. Those vastly improved latencies attained by 3D NAND flash memory stacks must not get compromised by data paths within various building blocks assembled in 2.5D or 3D systems in a package. Similarly, data and information generated by sensors need to be processed, interpreted, and transmitted through communication systems with high signal and power integrity.

The focus of this event was wafer-level packaging (WLP) and FOWLP technology. With the evolution of semiconductor manufacturing processes, minimum feature size decreases and functionality built into the die increases along with I/O count, and heat generation within the die often increases. FOWLP technology offers a practical and cost-effective solution by creating additional surface area around the semiconductor die where I/O terminals can be placed. Outward routing from the die is facilitated by adding a redistribution layer (RDL) structure having one or more routing layers.

Implementation of the systems noted above, often in application-driven form factors, presents formidable challenges to outsourced semiconductor and test suppliers (OSATS) and circuit and systems designers alike. Circuit and system performance can no longer be separated from the packaging technology deployed. As noted by several presenters at the conference, the new paradigm is a collaborative approach between circuit/system and package design teams. One of the speakers at a panel discussion cited an example of the exemplary collaboration between Apple's design teams and TSMC's developers of the highly advanced Integrated Fan-Out Wafer-Level Packaging (InFO-WLP) technology deployed in the A10 processor of the iPhone7.

Given this backdrop, in his keynote address, Prof. Rao R. Tummala of Georgia Institute of Technology discussed the future of fan-out wafer-level technologies and active/passive component embedding. In another keynote presentation, Prof. Klaus-Dieter Lang, Director of Fraunhofer IZM, outlined his vision of advanced manufacturing technology platforms required to serve the needs of a diverse field of cyber-physical systems. Dr. Lang highlighted an existing gap between wafer-panel and rectangular PCB-panel infrastructures in the 2-20µm L/S range and stressed the need to find reliable, low-cost solutions.

Panel discussions

Large-area rectangular panel processing. Participants of a panel discussion, moderated by Jan Vardaman of TechSearch International, examined the potential cost savings and existing barriers that large-area rectangular panel processing needs to overcome before 2.5D and 3D FOWLP system-in-package (SiP) structures having less than 20µm L/S could be fabricated in a high-volume manufacturing environment. Per estimates, most cost benefits stemming from increased throughput can be attained at a roughly 600mm x 600mm panel size. The larger the individual package size, the larger the saving. For example, at a 10mm x 10mm package size, a 25-30% cost reduction is realizable; however, at a 4mm x 4mm or smaller package size, there is no cost saving.

The need for optical systems having higher accuracy and depth of focus to accommodate processing of large warped wafers with high yield and reliability was discussed. The lack of standards and requirement for die-shift error correction were also highlighted. Panel processing plant tooling costs were estimated to be over $150 million. Panelists suggested that IoT and the requirement for processing massive amounts of data in the coming years ahead are likely to be the market driver that finally ushers fine-pitch fan-out panel-level packaging (FO-PLP) into mass production.

Chip-package interaction. Dr. Urmi Ray of Qualcomm moderated another panel discussion on chip-package interaction (CPI) and its impact on products fabricated for the commercial, automotive, and defense sectors. The discussion followed two paths: mechanical CPI (mCPI) and electrical CPI (eCPI). Many attendees asked specific questions concerning back-end-of-line (BEOL) separation, metal line breakage, warpage, die thinning, issues related to thick Cu RDL, advanced process nodes using ultra low-k materials, and new failure mechanisms. The long list of concerns underscored the need for consistent process control, predictive modeling, and tracking and understanding failure mechanisms.

Session highlights

Concerning session highlights, it is impossible to offer a comprehensive overview of so many excellent presentations in a short article, however a few are highlighted below.

Dr. Habib Hichri of SUSS MicroTec described a full-field scanning exposure system with a 1:1 projection lens suitable for high-resolution patterning and large depth of focus. These features and the 30x30mm field size are essential for working with thick photoresist and warped 300mm wafers or large rectangular panels. The system has closed-loop projection mask temperature control to facilitate use of low-cost soda lime masks. The system has software to correct for die placement errors, and it is capable of supporting less than 3µm L/S at 50% lower cost-of-ownership relative to UV steppers.

Eoin O' Toole of NANIUM S.A. addressed an emerging thermal challenge: as FOWLP is moving towards accommodating multiple dies in 2.5D and 3D package-on-package (PoP) forms, the dissipated power within the die increases. Consequently, thermal resistance of the new structure requires enhancement. The company addressed this issue in the form of a demonstrator project. The key point is the need to address this issue proactively.

Dr. Bora Baloglu of Amkor's described the company's multi-die capable and 3D PoP compatible high-density polymer-based chip last fan-out process that is expected to deliver lower cost and reduced z-height. This technology has a maximum of three layers of RDL with a 2-10µm L/S range. The target market is multi-die SoCs, high-bandwidth memories (HBM), mobile applications, and networking.

Eight presentations were devoted to manufacturing issues: Dr. Guilian Gao of Invensas disclosed a room-temperature Cu-Cu direct bond method initially developed for wafer-to-wafer (W2W) bonding that is already in high-volume production for image sensors. The technology was recently further developed for die-to-wafer (D2W) and die-to-die (D2D) stacking, positioned as a simpler alternative to thermal compression bonding of microbumps. Per Dr. Gao, this technique uses a unique grid-contact pattern that is more tolerant to D2D and D2W misalignment—an important consideration impacting both cost of production and cost-of-ownership. While the technique requires a less than 1nm surface roughness, this is within the capabilities of today's chemical mechanical polishing (CMP) technology she noted.

Four of the eight MEMS presentations described various low-temperature bonding methods to create a hermetic seal between a MEMS device wafer (DW), and a cap wafer (CW) using wafer-level bonding (WLB) process. The key requirements of this process are hermeticity sustained over time, a narrower bond-seal footprint, low peak process temperature, low bonding pressure, and a less than 2µm alignment capability. Eutectic and diffusion bonding techniques are the leading candidates.

Advances in various gold electroplating applications were described by Dr. Lynne Michaelson of Technic Inc., a provider of advanced plating equipment and specialty chemicals. The author presented images of remarkably outstanding results attributed to a proprietary additive.


IWLPC 2016 turned out to be a very well-attended three-day event. Conference organizers, invited speakers, authors of papers, and exhibitors all contributed to creating this lively, inspiring event, facilitating an informal exchange of ideas for learning and collaboration, all to the good of package engineering—a key enabling technology of our times.

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Organized by: SMTA and ChipScale Review

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IEEE Electronic Packaging Society

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