October 13 - 15, 2020
DoubleTree by Hilton San Jose
San Jose, California, USA

IWLPC 2019 Concludes Successfully

Save the Date for 2020!

IWLPC 2020:
October 13-15, 2020
San Jose, CA, USA

Submit an abstract for IWLPC 2020

Abstracts are currently being accepted if you would like to present at this conference. Technical papers and presentations are required and will be due April 3, 2020.

Click here to submit an abstract!

View the 2019 Technical Program

Interconnecting Wafer-Level Packaging, 3D Packaging, Advanced Manufacturing and Test, the International Wafer-Level Packaging Conference (IWLPC) is at the forefront of the packaging technology evolution.

The Wafer-Level Packaging (WLP) track features sessions on Advanced Wafer Level Packaging & Materials, Reliability and Metrology, Fan Out Wafer level Packaging (FO-WLP), and Advanced Processing.

The 3D Packaging track features sessions on Design, Characterization and Test, Wafer Bonding and Chip Stacking, and Processing for Fan-Out.

The Advanced Manufacturing track features sessions on Process Materials and Equipment.

View PDF program here!

View full album here!

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Organized by: SMTA and ChipScale Review

Supported by:
IEEE Electronic Packaging Society

Supporting Media:
MEPTEC Open Sky Communications