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October 13-16, 2008
Wyndham Hotel
San Jose, CA |
     
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The IWLPC is supported by
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IWLPC Workshops
Listed below are nine half-day workshops led by industry
professionals with extensive experience in their respective subject areas.
Workshop instructors deliver focused, in-depth presentations on topics of
current importance to the industry, based on their research and industry
experience.
Workshops are application oriented and
structured to combine field experience with scientific research to solve
everyday problems. They are offered on Monday, October 13 and Tuesday, October 14, preceeding the technical conference.
WS1 - IC Packaging Technology Evolution and Future Direction
WS2 - Solder Free Technology: The Next SMT?
WS3 - Test: A Semiconductor Manufacturing Process in Transition
WS4 - PoP Applications, Requirements, Infrastructure and Technologies
WS5 - Failure Modes & Analysis of Flip Chip Assemblies
WS6 - Packaging for MEMS, MOEMS and Nanoelectronics
WS7 - 3D IC Integration: An Emerging System-Level Architecture
WS8 - ESD/ESA Factory Issues & Equipment, Standards and Safeguards
WS9 - Surviving Pending Changes in U.S. Patent Law
WS1 - IC Packaging Technology Evolution and Future Direction Joseph Fjelstad, Verdant Electronics (Instructor Bio)
Monday, October 13: 8:00am - 12:00pm
What You Will
Learn IC packaging technology was at one time considered an unfortunate necessity. However, over the course of the last decade IC packaging has risen greatly in importance. Today, the IC package in all of its numerous manifestations is the gate keeper of much of the cost and performance of electronic systems.
This highly competitive sector of the electronics manufacturing infrastructure is also one of the most innovative and enabling. IC packaging has made possible the continuous reduction in cell phone size even as features dramatically increased. This workshop will trace the history of IC packaging technology from its simple beginnings to today's complex 3D structures that are extending the boundaries of the technology to new realms.
Topics Covered
IC assembly basics
IC package types and structures
Chip scale and wafer level packaging
3D assemblies
Testing requirements
Speculative crystal ball look into the future
WS2 -
Solder Free Technology: The Next SMT? Phil Marcoux (Instructor Bio)
Monday, October 13: 8:00am - 12:00pm
What You Will Learn
Solder, specifically tin-lead solder has served the electronics industry faithfully for decades. During the last two decades the industry has been trying to comply with government imposed directives calling for the elimination of lead. Sadly the lead solder replacements have issues making them less faithful than the tried and true tin-lead solders.
Over the past ten years, a number of alternative processes have been introduced that appear to provide an industry solution. These methods are completely solder free. They appear to eliminate other cost and environmental factors from the conventionally used SMT processes and materials.
The workshop will explore the processes which may define what the speaker terms the Solder Free Technology or SFT Era.
Topics Covered
What’s wrong with solder, any solder?
Early efforts to avoid solder
PCB first or PCB second?
Is WLCSP the ideal solder free component packaging?
Lessons from the evolution of SMT
Can we make this happen?
Who Should Attend
Anyone involved in creating, designing, and manufacturing electronic products
WS3 - Test: A Semiconductor Manufacturing Process in Transition Phil Burlison, Verigy Ltd. (Instructor Bio)
Monday, October 13: 1:00pm - 5:00pm
What You Will Learn
This workshop covers the area of semiconductor test and how is is changing. This change is being brought about by:
Expanding functional complexity of new ICs developed using the new nanometer technology
New failure mechanisms because of the new nanometer technology
The progress of DFT and BIST for more comprehensive test coverage
New System Level Packaging effecting the test access mechanisms
System level test requirements
The need for expanded yield learning and enhancement
WS4 - Package-on-Package (PoP) Applications, Requirements, Infrastructure and Technologies Moody Dreiza, Amkor Technology Inc. (Instructor Bio)
Monday, October 13: 1:00pm - 5:00pm
What You Will Learn
This course will help you decide when and how PoP technology can provide system level semiconductor integration benefits. How you can evaluate and select the optimum PoP technology for your applications by understanding the complex mix of cost, performance and business/logistic benefits PoP provides. Where industry standards, device floor-planning and supply chain infrastructures can reduce the total cost or time to market when implementing a PoP solution. How the PoP platform aligns with industry roadmaps to meet the higher density challenges associated with next generation device integration and system design requirements. What the key PoP design related parameters are and how they relate to package sizing and selection.
Topics Covered
The top PoP which is typically a memory component using stacked die multi-chip package technology to integrate a combination of memory devices
The bottom PoP which is typically a logic component using advanced high density thin core substrate technology with special design and material properties to enable integration of a high density mobile processor device and support stacking of combination memory top package
The PoP infrastructure - including SMT stacking, pre-stacking and joint industry studies for stacking and board level reliability testing
Real world high volume PoP applications used in multimedia mobile handsets based on industry teardown reports
The critical role industry infrastructure development and JEDEC standards have played in the high rates of PoP adoption in mobile multimedia applications
WS5 - Failure Modes & Analysis of Flip Chip Assemblies
Dr. Daniel F. Baldwin, Engent Inc. (Instructor Bio)
Tuesday, October 14: 8:00am - 12:00pm
What You Will Learn
Several material and process technology advances recently emerged for flip chip assembly processing such as fast-flow snap-cure underfills, no-flow underfills, emerging wafer scale underfills and associated innovative process technology. While a large number of technical publications help with understanding basic process requirements, understanding of failure modes and reliability standards remains essential for these technologies to gain traction in the industry. This course presents reliability test procedures, frequently encountered process defects and common failure modes that occur in flip chip packages and board level flip chip assemblies. The course focuses on accelerated reliability tests, process defect identification and resolution, failure mechanisms and the associated analysis tools needed to identify them such as FTIR, XRF, transmission X-ray analysis, acoustic microscopy and scanning electron microscopy. Descriptions of numerous process defects and failure modes presented along with extensive visual aids provide a more intuitive understanding of the defects and failure modes associated with these advanced assemblies. The course also discusses artifacts leading to process defects and how they contribute to premature failure.
Topics Covered
Reliability Tests
Destructive and Non-Destructive Failure Analysis and Equipment
Process Defects and Effects on Failure and Reliability
Reliability Modeling
Failure Modes and Reliability Implications
In Situ Stress Analysis of Flip Chip Assemblies
Who Should Attend
Target audience includes individuals and companies associated with electronics packaging; particularly package reliability, failure analysis, and assembly process control/defects. The content should prove especially valuable to:
Managers. Knowledge gained through this course will allow managers to make informed decisions about the technical feasibility, implementation factors, performance benefits, reliability, and risks of implementing flip chip technology.
Engineers. Manufacturing, quality, design, and packaging engineers in integrated circuit, equipment, materials, and system design who must solve process defect and packaging problems. Knowledge gained through this course will allow engineers and technologists to make informed decisions about the technical feasibility, implementation factors, performance benefits, reliability, and risks of implementing flip chip technology.
WS6 - Packaging for MEMS, MOEMS and Nanoelectronics
Dr. Ken Gilleo, ET-Trends LLC (Instructor Bio)
Tuesday, October 14: 8:00am - 12:00pm
What You Will Learn
This new-for-2008 workshop will provide a concise yet comprehensive view of MEMS (Micro-Electro-Mechanical Systems) and MOEMS (aka; optical-MEMS), with a brief look at emerging Nanoelectronics. 2008 will be the Year of MEMS, with more breakthroughs, product launches and accelerated market penetration. MEMS/MOEMS technology will be illustrated with diagrams, animations, photographs, videos, and live demos.
The theme is wafer-level MEMS assembly and packaging; and their unusual challenges. A variety of options are proposed, with the trade-offs for “really new” vs. traditional packaging. Packaging strategies are categorized by MEMS device/application; solutions are often product-specific. The status and availability of commercial packages is also reviewed with examples.
Future packaging trends are reviewed based on a patent survey with extensive figures. The workshop will also examine the requirements for nano-electronic device packaging -- and propose solutions -- even before the devices are commercialized!
Topics Covered
Device materials
3D structures
Fabrication
Actuation mechanisms
Operation
Product applications
Who Should Attend
Inventors, product developers, innovators, startup specialists, marketing personnel, business analysts, lawyers, equipment providers, futurists, and technologists in electronics, medical, biology, BioMed, analytical field, optoelectronics, materials, telecom systems, and military.
WS7 - 3D IC Integration: An Emerging System-Level Architecture
Dr. Phil Garrou, Microelectronic Consultants of North Carolina
Tuesday, October 14: 1:00pm - 5:00pm
What You Will Learn
The course will begin by defining and contrasting 3D Integration (thinning, bonding and TSV) to 3D packaging (thinning stacking and wire bonding to the BGA base). We will then look at the various drivers for 3D integration including the electrical performance and economic issues that are about to end device shrinkage as we know it, and the volumetric efficiency issues faced in today’s portable device. We will then look at the various proposed process sequences being proposed for 3D integration and the process unit operations necessary to fabricate a 3D stack.
The processes sequences proposed by Universities, Institutes and commercial entities will be compared and contrasted and then we will look at the applications expected to be the early adopters for 3D technology (CIS [CMOS image sensors]; memory [DRAM and NAND]; memory on logic and heterogeneous integration).
The course will end by looking the remaining technical and market barriers (design, thermal and test) and looking at the current best sources of 3D information.
Who Should Attend
The course will be aimed at technical personnel wanting a status review of the subject and marketing/management personnel looking for a status report to help determine their position in the business food chain.
WS8 - ESD/ESA Factory Issues & Equipment, Standards and Safeguards
Robert J. Vermillion, RMV Technology Group LLC (Instructor Bio)
Tuesday, October 14: 1:00pm - 5:00pm
What You Will Learn
In a very interactive format, the course study will cover Factory Issues and ESD/ESA Auditing & Validation Techniques, ESD/ESA Practices in the semiconductor, medical device, pharmaceutical delivery, defense, disk drive industry and consumer/retail level issues arising from a microprocessor driven marketplace.
Topics Covered
ESD Roadmap of Device Sensitivity and Microprocessor Densification Issues
Damage Models Relationship
Device Classifications and ESD Control Measures to Class 0
ESD Control in the Workplace for ANSI/ESD S20.20-2007 & ANSI/ESD S541-2003
ESD/ESA Advanced Monitoring Systems in the Workplace
Ionization
Material Qualification Sequence, How to Qualify Material from Suppliers?
Packaging Materials Selection
Value of Validation
Anticounterfeiting Measures for Packaging, Materials & Components
If You Don’t Validate, Expect Counterfeiting Hazards!
ESD/ESA Preventative Measures and Validation/Auditing Techniques at the Machine Center
ESD POLYMERS
Conductivity Properties
Surface and Volume Resistance Expectation for Polymer Types
Thermoforming Considerations for Achieving Excellent ESD Properties
ESD Testing Methods for Material and Packaging Design Structures
Who Should Attend
Quality Engineers, Manufacturing Engineers, Packaging Engineering, ESD Coordinators, Quality Control, Quality Assurance, Engineering Procurement, Equipment Engineering, Electronic Packaging Engineers.
WS9 - Surviving Pending Changes in U.S. Patent Law
A. Jason Mirabito and Carol Peters, Law Offices of Mintz Levin, Boston (Instructors Bios)
Tuesday, October 14: 1:00pm - 5:00pm
What You Will Learn
Sweeping changes in U.S. laws related to patents and the protection of intellectual property have been proposed in the Patent Reform Act of 2007, which is likely to become law this year. These changes will incorporate items such as “first to invent” versus “first to file,” bringing the U.S. to parity with most other nations.
Infringement damages, third-party submission of prior art and venue for litigation are a few of the other proposed changes.
Who Should Attend
This workshop, presented by two attorneys who specialize in patent, trademark and IP law, will be invaluable for lawyers and others, inventors for example, who will be dramatically affected by the changes.
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