Listed below are five half-day tutorials led by industry
professionals with extensive experience in their respective subject areas.
Tutorial instructors deliver focused, in-depth presentations on topics of
current importance to the industry, based on their research and industry
experience.
The IWLPC tutorials are application oriented and
structured to combine field experience with scientific research to solve
everyday problems. They are offered on Tuesday, October 27 and Wednesday, October 28, preceeding the technical conference.
T1 - Advanced Packaging Technologies and Future Interconnection Trends Joseph Fjelstad, Verdant Electronics (Instructor Bio)
Tuesday, October 27: 8:00am - 12:00pm
What You Will
Learn IC packaging technology is the first interconnection element supporting the semiconductor chip, and is the primary gatekeeper of electronic system performance. With so many packaging options available, understanding the basics of IC packaging is critical to successful product design. This course reviews common IC packages, including chip scale, BGA, 3-D stacked and folded packages. A review of wafer-level packaging and evolving TSV technologies is also covered.
Topics Covered
Roles of IC packaging
Construction and manufacturing processes for common IC packages
Impact of IC package design on the assembly processes
Testing strategies
Trends in the integration of IC, package and PCB substrate (e.g., the Occam Process)
What’s new, and where IC packaging technology is headed
Role of IC packaging technologies in electronics assembly
Chip scale packaging types
3-D packaging concepts
Reliability testing and electrical performance of CSPs
Impact of lead-free check points and alternative approaches
Standards for substrates
The future of IC packaging
T2 - Nanoelectronics, MEMS, and MOEMS - Products & Packages Ken Gilleo, Ph.D., ET Trends LLC (Instructor Bio)
Tuesday, October 27: 8:00am - 12:00pm
What You Will Learn
This tutorial provides a concise yet comprehensive survey of Nanotechnology, MEMS, and MOEMS (optical-MEMS). The tutorial highlights similarities, while showing fundamental differences, for the triad of technologies. While Nanotech is mostly emerging, MEMS is now at center stage with new design wins every week. And MOEMS is gathering momentum in projection displays, both very large and very small. MEMS is a top performer for Right Time Enabling Technology that uniquely solves today’s challenges in a clever way to provide differentiation for cool “must have” products like the iPhone that we’ll cover and demonstrate.
MEMS/MOEMS technology will be illustrated with diagrams, animations, photographs, videos, and live demos. The trend is wafer-level MEMS assembly and packaging (WLP); and the unusual challenges. A variety of options are proposed, with the trade-offs for “really new” vs. modified traditional packaging. Strategies are categorized by device/application and solutions are often product-specific. The status and availability of commercial packages is also reviewed with examples. Package topics include accelerometers, gyroscopes, silicon microphones, pressure sensors, fluidic-MEMS, Bio-MEMS, lab-on-chip, jetting chips, self-propelled MEMS, mirrors, and several others, including the strange. MOEMS packaging topics: sealing windows without adhesives, getters, and cost reduction vs. reliability. The pros and cons of chip-level vs. wafer-level today will be discussed. The tutorial will then look at new Nano-electronic devices and their packaging. Surprisingly, the package solutions may already be here, waiting for Nano-electronic devices!
Topics Covered
Materials
3D structures
Fabrication
Actuation mechanisms
Operation
Product applications
Who Should Attend
Inventors, product developers, innovators, startup specialists, marketing personnel, business analysts, lawyers, equipment providers, futurists, and technologists in electronics, medical, biology, BioMed, analytical field, optoelectronics, materials, telecom systems, and military.
T3 - Design for Wafer Level CSP Technology Vern Solberg, Solberg Technical Consulting (Instructor Bio)
Tuesday, October 27: 1:00pm - 5:00pm
What You Will Learn
The gap between printed boards and semiconductor technology (wafer level integration) is greater than one order of magnitude in interconnection density capability. Although the development of fine-pitch substrates and assembly technology has narrowed this gap somewhat, interconnecting miniature, finer pitch array components remains a challenge for designers. All viable efforts are being used in filling this void utilizing uncased wafer level packaged semiconductors as well as incorporating more than one die or more than one part in the assembly process.
Because of the higher component density made possible by adapting these newer generations of IC package technologies, assembly specialists have found that an optimized design layout, land pattern geometry refinement and the selection of quality substrate materials can have a positive affect on both manufacturing efficiency and product reliability. This tutorial provides a comparison of different commonly used technologies including flip-chip, chip-size and wafer level array package methodologies detailed in a new publication, IPC-7094. It considers the effect of bare die or die-size components in an uncased or minimally cased format, the impact on current component characteristics and reviews the appropriate PCB design guidelines to ensure efficient assembly processing.
Topics Covered
WLBGA and DSBGA standards
Wafer level and die-size packaging process methodologies
Land pattern requirements for WLBGA and DSBGA
Materials and methodology for high density circuit fabrication
Specifying PCB surface finish and coatings
Board level assembly process options
Who Should Attend
This tutorial has been developed specifically for PCB designers, design engineers and those responsible for electronic product development, assembly processing and manufacturing efficiency. This would include manufacturing and test engineering specialists for the OEM, ODM and EMS providers.
T4 - Advanced Flip Chip Technology and Processing Dan Baldwin, Ph.D., Engent, Inc. (Instructor Bio)
Wednesday, October 28: 8:00am - 12:00pm
What You Will Learn
Flip chip assembly technology is gaining increased acceptance in the electronics industry. Annual growth rates projected through the next decade are 40% or higher. While flip chip technology was developed over thirty years ago by IBM and has been in production on ceramic substrates, it has yet to achieve cost competitiveness with high volume semiconductor packaging and low cost surface mount technology. In order to achieve cost competitiveness, new and innovative material systems and process technologies are required.
This course presents advanced flip chip process technology focusing on first pass yield, throughput, and cost. The course includes extensive handouts covering advanced flip chip process technology and materials. Flip chip processing of solder interconnect system, conductive adhesive interconnect systems, thermosonic interconnects, and thermocompression interconnects will be presented. In addition, key processing elements such as underfill processing, reliability, and failure analysis will be presented. The relationship between process induced defects and flip chip reliability will be discussed. A comprehensive process characterization, reliability analysis, and failure mode analysis will be presented.
Topics Covered
Flip chip technology
Flip chip process fundamentals
Advanced flip chip process technologies
Conductive adhesive interconnect systems and processing
Flip chip process implementation
Reliability analysis and failure modes
Who Should Attend
Individuals associated with advanced surface mount assembly, bare die module assembly, and advanced electronics packaging are encouraged to attend, specifically, the following:
Managers. Knowledge gained through this course will allow managers to make informed decisions about the technical feasibility, implementation factors, performance benefits, reliability, and costs of implementing advanced flip chip processing technology.
Engineers. Manufacturing, quality, design, and packaging engineers in integrated circuit, equipment, materials, and system design who are challenged to solve tomorrow’s process solutions and next generation packaging problems.
T5 - 3D Packaging Applications, Requirements, Infrastructure and Technologies
Lee Smith, Amkor Technology (Instructor Bio)
Wednesday, October 28: 1:00pm - 5:00pm
What You Will Learn
This tutorial will help you decide when and how 3D package integration can provide system or component benefits. How to evaluate and select the optimum 3D package technology based on the complex mix of cost, performance and business/logistic requirements. Where industry standards, device floor-planning and supply chain infrastructures; can reduce the total cost or time to market when implementing a 3D solution. How 3D platform technologies and industry roadmaps can be projected or shaped for next generation device integration to system design requirements.
The instructor will give a summary of the surface mount process parameters for PoP stacking both single pass reflow and pre-stacking.
A method will be introduced for rating and ranking the adoption risks for new package technologies or supply chains. This method can be used as a tool for new technology adoption, component procurement or product development requirements.
A section of the tutorial will review real world high volume 3D package technologies used in multimedia mobile handsets. Quantify the technical and business/logistic requirements and trends that make up the total cost of ownership equation.
The tutorial will explore the critical role industry infrastructure and standards play in new 3D package platforms by summarizing the package on package collaboration efforts and results.
Topics Covered
MCP (multichip package) components using a combination of stacked, wire bonded memory die, also referred to as stacked die package or stacked CSP
SiP (system in a package) uses a combination of stacked logic and memory die with wirebonding or a mix of FC and wirebond interconnects
PoP (package on package) uses stacked packages where logic and memory components are produced separately and stacked in the OEM’s surface mount assembly flow
Embedded chip technologies where active or passive chips are embedded in printed wiring or thin film build up circuits with interconnect patterns on both sides
Wafer level 3D packaging including die on wafer, wafer on wafer and TSV approaches
TSV (thru silicon vias) where memory die are designed for thru Si via connection to enable multiple die to be stacked in a flip chip style assembly flow to increase memory capacity in the smallest/thinnest package profile
Listed below are five half-day tutorials led by industry
professionals with extensive experience in their respective subject areas.
Tutorial instructors deliver focused, in-depth presentations on topics of
current importance to the industry, based on their research and industry
experience. 