Two days of professional tutorials have instructors drawn from the pre-eminent authorities in their fields. Each tutorial represents an outstanding opportunity to meet with your peers in a relaxed atmosphere for an intensive course mentored by an expert.
The IWLPC tutorials are application-oriented and
structured to combine field experience with scientific research to solve
everyday problems. They are offered on Monday, October 11 and Tuesday, October 12.
T1 - Three Dimensional Assembly, Packaging & Integration
Chuck Bauer, Ph.D., TechLead Corporation - Instructor Bio
Monday, October 11, 2010: 1:30pm - 5:00pm
What You Will Learn:
The latest trend in miniaturization of electronics systems, 3D assembly and packaging of both active and passive devices opens a new world of performance and integration to system designers. This course covers both the fundamental and advanced technologies in use today to produce stacked chip packages as well as stackable packages for implementation of highly integrated mobile electronic products. These include the challenges of die thinning, thin die attach, multi-level wire bonding, mixed technology die attachment and bonding, flip chip, TAB and TSV (Through Silicon Via) technologies. Substrate selection for various 3D packaging techniques including silicon tiles, flex circuit origami and specialty interposers concludes the chip stacking section of the course. Several examples of specific 3D package structures demonstrate both the power and limitations of these approaches.
Further considerations for 3D electronics include stackable packages based on flex and rigid substrate approaches, integrated system in package (SiP) techniques and multilayer, embedded passive technologies. Additional coverage of SMT design and assembly implications rounds out the technical content of the course. The course concludes with a review of the drivers behind 3D packaging and presentation of multiple examples of 3D packages in actual usage today.
Topics Covered:
3D Package Trends
3D Package Applications
Stacked Packages
Package on Package
Origami
Edge Stacked Modules
Die Stacking
Wire Bond
Mixed Technology
Edge Redistribution
Through Silicon Vias
3D Integration (SiP)
Issues in 3D Integration
SMT Assembly Implications
Drivers for 3D Packaging
Intellectual Property Landscape for 3D Packaging
Who Should Attend:
This course covers basic and advanced topics for product and design engineers, manufacturing process and assembly/packaging engineers, engineering managers, senior design technicians, consultants and academic specialists as well as marketing and sales personnel requiring an understanding of the capabilities, implications and options of 3D packaging and assembly technologies.
T2 - Advanced Packaging Technologies and Future Interconnection Trends
Joseph Fjelstad, Verdant Electronics, Inc. - Instructor Bio
Monday, October 11, 2010: 1:30pm - 5:00pm
What You Will Learn:
IC packaging technology is the first interconnection element supporting the semiconductor chip, and is the primary gatekeeper of electronic system performance. With so many packaging options available, understanding the basics of IC packaging is critical to successful product design. This course reviews common IC packages, including chip scale, BGA, 3-D stacked and folded packages. A review of wafer-level packaging and evolving TSV technologies are also covered.
Topics Covered:
Roles of IC packaging
Construction and manufacturing processes for common IC packages
Impact of IC package design on the assembly processes
Testing strategies
Trends in the integration of IC, package and PCB substrate (e.g., the Occam Process)
What’s new, and where IC packaging technology is headed
Role of IC packaging technologies in electronics assembly
Chip scale packaging types
3-D packaging concepts
Reliability testing and electrical performance of CSPs
Impact of lead-free check points and alternative approaches
Standards for substrates
The future of IC packaging
T3 - Wafer Level Packaging
Luu Nguyen, National Semiconductor Corporation - Instructor Bio
Tuesday, October 12, 2010: 8:30am – 12:00pm
What You Will Learn:
This course will provide an overview of the Wafer Level-Chip Scale Packaging (WL-CSP) technology. The market drivers, benefits, and challenges facing industry-wide adoption will be discussed. Typical WL-CSP configurations (bump on pad, bump on polymer, fan-out) will be reviewed in terms of their construction, manufacturing processes, and electrical and thermal performance, together with package and board level reliability.
Since the technology marks the convergence of fab, assembly, and test, discussion will address questions such as:
Does it fit best with front-end or back-end processing?
Will it be applicable and cost-effective for memory and other complex devices such as ASICs and microprocessors?
Are the current standards for design rules, outline, and reliability applicable?
Extensions to higher pin count packages and other arenas such as RF and MEMS will be reviewed. Future trends will also be covered such as enhanced lead-free solder balls, large die size, wafer level underfill, thin and ultra thin WL-CSP, RDL (redistribution layer), stacked WL-CSP, MCM in “reconstituted wafers,” embedded components, etc.
Who Should Attend:
The course will be useful to the following groups of engineers:
Newcomers to the field who would like to obtain a general overview of WL-CSP.
R&D practitioners who would like to learn new methods for solving CSP problems, and considering WL-CSP as a potential alternative for their packaging solutions.
T4 - 3D Packaging and WLP Evolution and Trends: Technology, Market, Supply Chain Infrastructure
Jean-Marc Yannou, Yole Développement Instructor Bio
Tuesday, October 12, 2010: 8:30am – 12:00pm
What You Will Learn:
Since the advent of photolithography in electronics in the early sixties, and for decades, most new technology developments for the semiconductor industry have aimed at downsizing the transistors so as to make more integrated, more powerful, faster and even cheaper Integrated Circuits (ICs). In the past few years, this industry has changed and this in turn shifted the paradigm of technology innovation for semiconductors: a consensus is rising within the community of process experts and scientists that further downsizing of the transistors will not only become more difficult because new geometries tend to the physical limit of atom sizes, but it will also come along with lower performance side-effects such as higher parasitic coupling, higher current leakage and thermal issues. From an investors’ perspective, the math is simple: in order to reach the next CMOS technology node, huge investments are needed, and the expected benefits are still unclear. In parallel, electronic applications are being thought differently and processing power is now less seen as an end than as a means to develop and build user-friendly communicating personal devices and appliances.
You do not only want a game console with bright and fast high resolution graphics. You now want to interact with it: it can feel and sense you in every possible way, by means of motion and video sensors. Patients with cardiac rhythm malfunctions want to enjoy their lives as they did before being equipped with a pacemaker: continuous monitoring is now made possible as the pacemaker device measures the heart beats and directly sends relevant information via the patients cell phone to his physician without requiring any formal examination at the doctor’s. As a consequence, there is rising awareness that integrated circuits are increasingly interacting with the real world by receiving, processing and transmitting more information than ever before. The focus is shifting from the transistors constituting the integrated circuits to their external interfaces, from processors to sensors and actuators, from circuits to systems: the value of semiconductors is shifting from ICs to IC and system packaging.
But the challenges remain the same as 50 years ago: how to make high performance, fast, low consumption and cheap highly integrated electronic systems? What is changing is how this is now increasingly being addressed. And the answer stands in a few keywords: mid-end, wafer-level packaging, 3D integration. The whole idea is to pack more electronic function per volume unit (instead of surface area) and to extend the photolithography techniques beyond the making of ICs to their packaging and their integration in a system. And this is a heavy trend: Yole forecasts that from slightly less than M$500 in 2010, the market of 3D integration using through silicon vias (TSV) will grow to more than B$4 in 2015, addressing a wide variety of advanced systems! Packaging of MEMS and sensors using wafer-level techniques will become mainstream in just a few years as we forecast a compound annual growth rate of 85% over the 2009-2013 time period!
Throughout this tutorial, we will rehearse the evolution of wafer level packaging techniques and applications over the past 5 to 10 years, and we will replace this evolution in the context of the evolution and history of semiconductor packaging. We will then review the latest technology developments including WLCSP, fan-out WLCSP, chip embedding, 3D ICs and 3D glass/silicon interposers, and we will review those applications where these technologies are most likely to cause deep changes of the packaging environment. We will review Yole’s latest market forecasts for these emerging packaging technologies and we will consider how deeply these are and will be changing the IC packaging supply chain infrastructure.
T5 - Advanced Flip Chip Technology and Processing
Daniel F. Baldwin, Ph.D., Engent, Inc. - Instructor Bio
Tuesday, October 12, 2010: 1:30pm - 5:00pm
What You Will Learn:
Flip chip assembly technology is gaining increased acceptance in the electronics industry. Annual growth rates projected through the next decade are 40% or higher. While flip chip technology was developed over thirty years ago by IBM and has been in production on ceramic substrates, it has yet to achieve cost competitiveness with high volume semiconductor packaging and low cost surface mount technology. In order to achieve cost competitiveness, new and innovative material systems and process technologies are required.
This course will presents advanced flip chip process technology focusing on first pass yield, throughput, and cost. The course includes extensive handouts covering advanced flip chip process technology and materials. Flip chip processing of solder interconnect system, conductive adhesive interconnect systems, thermosonic interconnects, and thermocompression interconnects will be presented. In addition, key processing elements such as underfill processing, reliability, and failure analysis will be presented. The relationship between process induced defects and flip chip reliability will be discussed. A comprehensive process characterization, reliability analysis, and failure mode analysis will be presented.
Topics Covered:
Flip Chip Technology
Flip Chip Process Fundamentals
Advanced Flip Chip Process Technologies
Flip Chip Processing With No Flow Underfill
3D Wafer Level Flip Chip Processing
Flip Chip Processing Based on Fast Flow Snap Cure Underfills
Fluxless Flip Chip Process Technology
Lead Free Solder Flip Chip Processing
Flip Chip Processing with Reworkable Underfills
Conductive Adhesive Interconnect Systems and Processing
Flip Chip Process Implementation
Reliability Analysis and Failure Modes
Who Should Attend:
Individuals associated with advanced surface mount assembly, bare die module assembly, and advanced electronics packaging are encouraged to attend, specifically, the following:
Managers. Knowledge gained through this course will allow managers to make informed decisions about the technical feasibility, implementation factors, performance benefits, reliability, and costs of implementing advanced flip chip processing technology.
Engineers. Manufacturing, quality, design, and packaging engineers in integrated circuit, equipment, materials, and system design who are challenged to solve tomorrow’s process solutions and next generation packaging problems.
T6 - Main Challenges & Key Technologies for 3D Integration
David Henry, CEA-LETI MINATEC - Instructor Bio
Tuesday, October 12, 2010: 1:30pm - 5:00pm
What You Will Learn:
3D integration is now clearly becoming a key technology for the future of the electronic components and systems. Actually, the 3D integration allows to decrease the form factor and the cost of the final device and to improve the electrical and thermal performances. We can distinguish two different approaches for 3D Integration, corresponding to two different business models. On one hand packaging companies will look for generic technologies, which can be applied on chips coming from different sources. 3D stack will be in that case achieved thanks to interconnections outside the silicon. On the other hand, silicon foundries which have a direct access to design and can adapt front-end processes, will use the possibility to perform Through Silicon Vias (TSV) to achieve ultra compact /low cost assemblies.
In this course, the different approaches will be presented. Then, a focus will be done on the main challenges to solve in order to transform the 3D integration from a concept to an industrial reality. In this part, the key technologies needed to succeed the 3D integration will be presented and detailed.
In the last part of the course, the different integration schemes and the main applications will be described. Finally, last trends will be given about the future of the 3D integration.
Topics Covered:
Introduction
General introduction
Main 3D actors & localisations
3D classification
The different 3D approaches
Main challenges for 3D
Design
Simulation / modeling
Metrology
Electrical tests
Key technologies for 3D
TSV first
TSV last - mid density
TSV last - high density
Interconnection technologies
Bonding technologies
Thin wafer handling + debonding
Components stacking / Underfilling
WLP : RDL + Bumping or balling
Rebuilt wafers
3D Integration schemes
3D TSV approaches
TSV free approaches
Si Interposers / Si package
3D applications
CIS : from 2.5 D to 3D
Heterogeneous integration
Homogeneous integration
Components partioning
The future of 3D integration
Conclusion
Who Should Attend:
Technologists: People involved in technology (processes & integration) and who need technological information on 3D different approaches.
Designers: People involved in 3D integration design and who need to have an overview of 3D integration available technologies.
Marketing staff: People who define new applications using 3D integration and who need cost evaluation based on process flows and integration schemes.
Managers: People involved in strategic decision and who need to have some roadmaps on different technologies for 3D integration.
