The IWLPC tutorials are application-oriented and
structured to combine field experience with scientific research to solve
everyday problems. They are offered on Monday, November 6 and Tuesday, November 7.
TSV and Other Key Enabling Technologies for 3D IC/Si Integration
John H. Lau, Ph.D., Industrial Technology Research Institute (ITRI)
Monday, November 5, 2012 | 8:30am-12:00pm
3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration, which will be discussed in this course. Emphases are placed on the key enabling technologies for 3D IC/Si integrations, such as TSV (through-silicon via) forming and filling, front and back-side metallization, RDL (redistribution layer), IPD (integrated passive devices), temporary wafer bonding, wafer thinning and handling, wafer de-bonding, thin chip/wafer strength measurement and improving, W2W bumpless bonding, lost-cost lead-free microbumping and assembly, low-temperature wafer bumping and C2C, C2W, and W2W bonding, and thermal management. Useful characterization and reliability data for 3D IC integration will also be provided. The application of 3D IC integration such as CMOS image sensor, MEMS, LED, memory + logic, logic + logic, memory + microprocessor, active and passive interposers will be presented. More than 15 companies' passive interposes (samples) used as substrates, carriers, and thermal management tools will be presented and discussed. Furthermore, the critical issues of TSV and 3D IC integration will be given and some potential solutions or research topics will be recommended. Finally, TSV manufacturing yield and hidden costs will be discussed and several roadmaps of 3D IC/Si integration will be provided. All the materials are based on the technical papers and books published within the past 3 years by the lecturer and others.
Who Should Attend?
If you (students, engineers, and managers) are involved with any aspect of the electronics, LED, MEMS, and optoelectronic industry, you should attend this course. It is equally suited for R&D professionals and scientists. You will receive more than 250 pages of handouts from the Instructor's books, "Advanced MEMS Packaging" (McGraw-Hill, 2010), "Reliability of RoHS Compliant 2D & 3D IC Interconnects" (McGraw-Hill, 2011), and TSV for 3D Integration (McGraw-Hill, 2012).
Instructor Biography Dr. John Lau has been an ITRI Fellow of Industrial Technology Research Institute (ITRI in Taiwan) since January 2010. Prior to that, he was a visiting professor at HKUST for 1 year, the Director of MMC Laboratory with IME in Singapore for 2 years and a Senior Scientist/MTS at HPL/Agilent in California, US for more than 25 years. With more than 35 years of R&D and manufacturing experience, he has published more than 350 peer-reviewed papers, 30 issued and pending US patents, given 270 lectures/workshops/keynotes worldwide, published 16 textbooks on 3D MEMS packaging, 2D and 3D IC integrations, flip chip & WLP, high-density PCB, SMT, and lead-free materials, soldering, manufacturing and reliability. John earned his PhD degree from the University of Illinois, 3 MASc degrees in North America. John received many awards, e.g., the best IEEE/ECTC Proceedings paper (1989) award, best ASME Transactions paper (Journal of Electronic Packaging, 2000) award, best IEEE Transactions paper (in CPMT, 2010) award, ASME/EEP Outstanding Technical Achievements award, IEEE/CPMT Manufacturing award, Outstanding Contribution award, and Outstanding Sustained Technical Contribution award. SME Total Excellence in Electronics Manufacturing award, and IEEE Meritorious Achievement in Continuing Education award. He is an elected ASME Fellow and has been an IEEE Fellow since 1994.
Luu Nguyen, Ph.D., Texas Instruments Inc.
Tuesday, November 6, 2012 | 8:30am-12:00pm
This course will provide an overview of the Wafer Level-Chip Scale Packaging (WL-CSP) technology. The market drivers, end applications, benefits, and challenges facing industry-wide adoption will be discussed. Typical WL-CSP configurations (bump on pad, bump on polymer, fan-out) will be reviewed in terms of their construction, manufacturing processes, materials and equipment, and electrical and thermal performance, together with package and board level reliability. Since the technology marks the convergence of fab, assembly, and test, discussion will address questions on the industrial supply chain such as:
Does it fit best with front-end or back-end processing?
Will it be applicable and cost-effective for memory and other complex devices such as ASICs and microprocessors?
Are the current standards for design rules, outline, and reliability applicable? Extensions to higher pin count packages and other arenas such as RF and MEMS will be reviewed.
Future trends will also be covered such as enhanced lead-free solder balls, large die size, wafer level underfill, thin and ultra thin WL-CSP, RDL (redistribution layer), stacked WL-CSP, MCM in "reconstituted wafers," embedded components, etc.
Who Should Attend?
The course will be useful to the following groups of engineers: Newcomers to the field who would like to obtain a general overview of WL-CSP. R&D practitioners who would like to learn new methods for solving CSP problems, and considering WL-CSP as a potential alternative for their packaging solutions.
Andy Oliver, Ph.D., Wireless Integrated MicroSensing and Systems Research Center (WIMS2)
University of Michigan
Tuesday, November 6, 2012 | 1:30pm-5:00pm
The course addresses techniques for packaging MEMS devices (wafer level and die), packaging equipment, and device testing. Specific examples of MEMS packages will be used to illustrate the design criteria, and processes for MEMS devices. Two major functional types of MEMS packages are sealed and open devices and the course will be divided into two sections.
Packaging for sealed MEMS devices - This section addresses the MEMS packaging processes that are enablers for sealed devices such as inertial sensors, optical devices, and MEMS actuators. Another emphasis will be implanted biomedical devices where Michigan has nearly 40 years of experience. Examples of MEMS systems will be used to illustrate the packaging challenges and solutions. Packaging for open MEMS devices - This section addresses the MEMS packaging methods for pressure sensors and environmental sensors. In these instances, the transduction element needs to be exposed to the measurand while protecting the electronics. Examples will include pressure sensors, flow sensors, gas sensors and micro gas chromatographs.
The course not only draws upon the experience of the presenter but will also incorporate material from the WIMS2 research center at the University of Michigan including Professors Khalil Najafi, Kensall Wise, and Yogesh Gianchandani.
Who Should Attend?
Product design engineers and engineering managers of MEMS device manufacturers who want to better understand MEMS packaging and the options available. Engineers, managers, and system designers who incorporate MEMS devices in their product and want to understand how to utilize the devices and manage their supply base. Researchers who want a summary of some of the latest packaging research from the University of Michigan.
Instructor Biography Andrew "Andy" Oliver has worked in MEMS for twenty years and in MEMS packaging for the past twelve. At Sandia National Laboratories in Albuquerque, he developed a wafer level packaging process for the SUMMiTTM surface micromachining process. Later, he developed a vacuum wafer level packaging processes at ICx Photonics for their MEMS infrared gas detector and acted as the technical interface for the wire bonding, die attach and encapsulation operations. His other professional experiences include SBIR based companies and startups. In 2011, he joined the University of Michigan's Center for Wireless Integrated MicroSensing and Systems as an Industrial Liaison and Principal Staff Scientist. He is an experienced instructor and has taught several courses on MEMS and MEMS packaging including a graduate level three credit course at the University of New Mexico and short courses for Sandia National Laboratories, the Boston section of IEEE, and at the COMS 2011 Conference. His writings have appeared in books that include MEMS Packaging, The MEMS Handbook, and The CRC Mechanical Engineering Handbook as well as numerous journal and conference papers.
Failure Mode Analysis of Flip Chip and Advanced Package and Board Assemblies
Dan Baldwin, Ph.D., Engent, Inc.
Tuesday, November 6, 2012 | 1:30pm-5:00pm
Over the past few years, numerous advanced packaging and process technologies have emerged such as flip chip in package, PoP, SiP, WLCSP, 3D-WLCSP, QFN, etc.. While a large number of technical publications are available to help with process requirements, understanding failure modes and reliability standards is essential for these technologies to be successfully sustained in production. This course will present reliability test procedures, assembly process defects, and common failure modes that occur in advanced package and board level assemblies. It will focus on process defect identification and resolution, failure mechanisms and the associated analysis tools needed to identify them such as FTIR, XRF, transmission X-ray analysis, acoustic microscopy and scanning electron microscopy. Numerous process defects and failure modes will be presented along with extensive visual aids to provide a more intuitive understanding of the defects and failure modes associated with these advanced assemblies. It will also discuss artifacts leading to process defects and how they can contribute to premature failure.
Who Should Attend?
Individuals associated with electronics packaging, package reliability, package failure analysis, and assembly process control/defects are encouraged to attend. Knowledge gained through this course will allow managers to make informed decisions about the technical feasibility, implementation factors, performance benefits, reliability, and risks of implementing flip chip technology. Manufacturing, quality, design, and packaging engineers in integrated circuit, equipment, materials, and system design who are challenged to solve process defects and packaging problems. Knowledge gained through this course will allow engineers and technologists to make informed decisions about the technical feasibility, implementation factors, performance benefits, reliability, and risks of implementing flip chip technology.
Instructor Biography Daniel F. Baldwin Ph.D., is the President of Engent, Inc. providing enabling process technologies and manufacturing services in the areas of electronics, optoelectronics, and MEMS. He was formerly the Vice President of the Advanced Assembly Technology Division at Siemens Dematic Electronic Assembly Systems. He also holds an Associate Professor of Mechanical Engineering position at the Georgia Institute of Technology heading the Low Cost Flip Chip Processing program for the Packaging Research Center, the Advanced Interconnect Technologies research program for the Manufacturing Research Center, and the Low Cost Assembly Processing Program for the CBAR. Dr. Baldwin received his S.M. and Ph.D. degrees in Mechanical Engineering from MIT in 1990 and 1994, respectively. He has eleven years of experience in the electronics manufacturing and polymer processing industries, four U.S. Patents, over 100 scholarly publications, and expertise in electronics packaging, MEMS packaging, advanced materials processing and manufacturing systems design. Dr. Baldwin is on the Board of Advisors for the Society of Manufacturing Engineers/Electronics Manufacturing Division (SME/EM) and serves as the president of the Surface Mount Technology Association (SMTA).