October 22 - 24, 2019
DoubleTree by Hilton San Jose
San Jose, California, USA

IWLPC Technical Committee

If you are interested in being part of the technical committee, contact IWLPC, iwlpc@iwlpc.com or 952-920-7682.

3D Integration

John Lannon

Co-Chair: John Lannon, Ph.D., Micross Advanced Interconnect Technology

Dr. John Lannon is the General Manager of Micross Advanced Interconnect Technology, a business unit of Micross focused on wafer-level advanced packaging, interconnect, and device integration technologies. Since receiving his Ph.D. degree in Physics from WVU in 1996, he has worked on the development of thin film materials and advanced packaging processes (e.g. high density interconnects, TSV integration, and wafer-level vacuum packaging) for next generation microsystems in sensor and scene projector applications.




Laurette Nacamulli

Laurette Nacamulli, The Dow Chemical Company

Laurette Nacamulli is Strategic Account Manager for Dow Chemical Electronic Materials – Advanced Packaging Technologies where she is responsible for promoting Dow’s packaging portfolio consisting of metallization and polymers. Laurette holds a BS in Chemistry and MS in electrochemistry both from Tel Aviv University, Israel. Previously, Laurette was a senior process engineer at Intel and held positions at Igen and Technicon developing electrochemical methods for diagnostics. She has authored papers and has a patent on electrochemiluminescence.




Herb Reiter, eda 2 asic Consulting, Inc.

After more than 20 years in technical and business roles at ASIC vendors and EDA software companies, Herb founded eda2asic Consulting, Inc. in 2002. Initially he focused on business development work to introduce products and services developed by mostly smaller EDA firms to major ASIC vendors. He introduced tools and IP for simplifying and accelerating SoC design efforts for integrating single die solutions into IC packages. Herb earned MSEE and MBA degrees in Austria/Europe, an MBA at San Jose State University and has attended 40+ Continuing Education Classes at Stanford University.





Wafer-Level Packaging

Saurabh Nilkanth Athavale

Chair: Saurabh Nilkanth Athavale, Ph. D., Maxim Integrated Products

Saurabh holds a Master’s degree in mechanical engineering and Doctoral degree in Industrial and Systems Science from State University of New York (Binghamton University). He has over 10 years of experience in the semiconductor industry and is currently involved in development of advanced wafer level packaging and board level reliability activities.




Tom Strothmann

Co-Chair: Tom Strothmann

Tom Strothmann is the former Director for Advanced Packaging Next-Generation Products at Kulicke & Soffa Industries, Inc. Prior to joining K&S, Tom managed Wafer Level Products Business Development for STATS ChipPAC, including Fan-In and Fan-Out WLP. Before STATS ChipPAC, Tom was Vice President of Business Development at FlipChip International and responsible for the formation of FlipChip Millennium Shanghai Co. At FlipChip Technologies, Tom successfully managed the transfer of bumping technology and the startup of bump lines for all major OSATS. Tom has 20 years’ experience in technology development for wafer bumping and related Advanced Packaging technologies and extensive experience in front end semiconductor manufacturing.




Tanja Braun, Fraunhofer IZM






Bora Bagaliou, Amkor






Jacinta Aman Lim, StatsChip Pac






Timo Henttonen, Microsoft






Jan Vardaman

Jan Vardaman, TechSearch International, Inc.

Jan Vardaman is the editor of Surface Mount Technology: Recent Japanese Developments, co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbun), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center study team involved in investigating electronics manufacturing in Asia and on the US mission to study manufacturing in China. She is a member of IEEE CPMT, IMAPS, SMTA, and SEMI. She was elected to two terms on the IEEE CPMT Board of Governors. She received her BA in Economics and Business from Mercer University in Macon, Georgia in 1979 and her MA in Economics from the University of Texas at Austin in 1981.





Advanced Manufacturing & Test

Garrett Oakes

Chair: Garrett Oakes, EV Group

Garrett Oakes is the Director of Technology for EV Group North America in Tempe, Arizona. Since joining EV Group in 2006, he has held positions in Strategic Sales and Applications Engineering. In his current role, he is responsible for the day-to-day operations of the applications lab and managing the efforts of the engineering organization. Prior to EVG, he spent eleven years as a photolithography process and development engineer for IBM and Hitachi in their storage technology divisions. Garrett holds a degree in Chemical Engineering from the University of California at Davis. He also holds several U.S. patents on the subject of temporary bond and debond for back end wafer processing.




Shekar Krishnaswamy

Co-Chair: Shekar Krishnaswamy, Applied Materials

Shekar has over 27 years of experience in all aspects of semiconductor manufacturing including wafer fab manufacturing, assembly and test. He started his career in IBM-Fishkill working in the advanced packaging segment focused on manufacturing multi-layer ceramic packages. His specific areas of expertise include traditional Industrial Engineering methods as well as systems related methodologies such as modeling, scheduling, dispatching and factory automation. Shekar has held senior technical and management positions at IBM, Motorola and AMD including management of corporate Operations Research departments supporting factory and service groups. Shekar has a Bachelor’s degree in Mechanical Engineering and a Master’s degree in Industrial Engineering and Operations Research.




Dale Gee

Dale Gee

Dale holds a Bachelor's Degree in Chemical Engineering from UC Berkeley, and an MBA from Santa Clara University. Dale began his career at Motorola Semiconductors in 1982 as a Device Engineer and throughout the 1980s, 1990s, and 2000s held various engineering, management, and executive positions with integrated circuit, sensor, and MEMS companies including Hewlett-Packard, Foxboro/ICT, Nayna Networks, Symyx Technologies, Visyx Technologies, GE Sensing, and Amphenol-NovaSensor, where he held the position of Sr. Global Product Manager.




Habib Hichri

Habib Hichri, SÜSS MicroTec Inc.

Habib Hichri joined SUSS MicroTec on October 2013 as Engineering Applications Director in Corona CA, USA. Before joining SUSS MicroTec, Habib spend about 12 years with IBM Semiconductors Research and Development Center in East Fishkil, NY where he worked as lead process integration engineer for microprocessor (IBM), games and communications chips. He later was promoted to management position within IBM on process development in lithography and Dry Reactive Ion Etch in the front end of line area for microprocessor fabrication. Habib holds over 35 U.S. patents and authored over 30 publications and presentations. Habib received Master and PhD degrees in Chemical Engineering from the Claude Bernard University at Lyon, France and an MBA degree from the State University of New York at Buffalo.








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Organized by: SMTA and ChipScale Review



Supported by:
IEEE Electronic Packaging Society Panel Level Packaging Consortium

Supporting Media:
MEPTEC Open Sky Communications