IWLPC Technical Committee
If you are interested in being part of the technical committee, contact Jenny Ng, email@example.com or 952-920-7682.
General Chair: Curtis Zwenger, Amkor Technology
Curtis holds a degree in mechanical engineering from Colorado State University and an MBA from the University of Phoenix. He has over 20 years of experience in the semiconductor industry and is currently responsible for the development and commercialization of Amkor’s Advanced Wafer Level Fan-Out and Glass Substrate product lines. Curtis joined Amkor in 1999 and has held leadership roles in developing Amkor’s Fine Pitch Copper Pillar, Through Mold Via, and MEMS packaging technologies. Prior to joining Amkor, he worked for Motorola.
Curtis has published several papers and has 12 patents related to semiconductor package engineering.
Technical Chair: Chris Scanlan, Deca Technologies
Chris Scanlan has been Vice President of Product Management and Engineering at Deca Technologies since the company was founded in November 2009. Mr. Scanlan is responsible for design and development of Deca’s advanced wafer level packaging technologies and well as the development of Deca’s portfolio of intellectual property. He has been the lead inventor of Deca’s WLFO technology, including the M-Series fan-out package structure and Adaptive Patterning™ dynamic lithography technology. Prior to joining Deca Technologies, Mr. Scanlan was Vice President of Applications Engineering for Amkor Technology. During his 10 years at Amkor, he held senior leadership positions in advanced technology development including Vice President of Global R&D, Vice President of the Advanced Products Business Unit, and Vice President of the System-in-Package Business Unit. Mr. Scanlan has more than 40 US patents related to advanced semiconductor packaging.
Chair: Laurette Nacamulli, The Dow Chemical Company
Laurette Nacamulli is Strategic Account Manager for Dow Chemical Electronic Materials – Advanced Packaging Technologies where she is responsible for promoting Dow’s packaging portfolio consisting of metallization and polymers. Laurette holds a BS in Chemistry and MS in electrochemistry both from Tel Aviv University, Israel. Previously, Laurette was a senior process engineer at Intel and held positions at Igen and Technicon developing electrochemical methods for diagnostics. She has authored papers and has a patent on electrochemiluminescence.
Co-Chair: Peter Ramm, Ph.D., Fraunhofer EMFT
Peter Ramm is head of the department Heterogeneous System Integration of Fraunhofer EMFT in Munich, Germany. He received his masters in physics and Dr. rer. nat. degrees from the University of Regensburg and subsequently worked for Siemens in the DRAM facility. Since 1988 he works for Fraunhofer, focusing on Si Technology, Devices and 3D Integration. Peter Ramm is co-author of over 100 publications and 24 patents. He is co-editor of Wiley's "Handbook of Wafer Bonding" and Wiley's series "Handbook of 3D Integration".
Arun Aiyer, Ph.D., Anjay Technology
pr. Arun Aiyer obtained his graduate degree from Indian Institute of Technology in Madras, India and his doctoral degree from University of Hull in the UK. Before coming to the semiconductor industry; Dr. Aiyer was with the Aerospace industry including the Jet Propulsion Laboratory. Since joining the semiconductor industry, he has been involved in the development of various wafer metrology and wafer inspection tools. He has twenty one patents to his credit. At present Dr. Aiyer is the CTO of Anjay Technology.
John Lau, Ph.D., ASM Pacific Technology
John H. Lau has been a Senior Technical Advisor of ASM since July 2014. Prior to that, he was a Senior Scientist/MTS at HPL/Agilent in California, US for more than 25 years. With more than 37 years of R&D and manufacturing experience, he has authored more than 435 papers, 30 issued and pending patents, given more than 280 lectures/workshops/keynotes worldwide, and authored 20 textbooks in semiconductor packaging.
Amandine Pizzagalli, Yole Développement
Amandine Pizzagalli is in charge of equipment & material fields for the Advanced Packaging & Manufacturing team at Yole Développement, the "More than Moore" strategy consulting and market research company, after graduating as an engineer in Electronics, with a specialization in Semiconductors and Nano Electronics Technologies. She worked in the past for Air Liquide with an emphasis on CVD and ALD processes for semiconductor applications.
Herb Reiter, eda 2 asic Consulting, Inc.
After more than 20 years in technical and business roles at ASIC vendors and EDA software companies, Herb founded eda2asic Consulting, Inc. in 2002. Initially he focused on business development work to introduce products and services developed by mostly smaller EDA firms to major ASIC vendors. He introduced tools and IP for simplifying and accelerating SoC design efforts for integrating single die solutions into IC packages. Herb earned MSEE and MBA degrees in Austria/Europe, an MBA at San Jose State University and has attended 40+ Continuing Education Classes at Stanford University.
Tom Strothmann, Kulicke & Soffa
Tom Strothmann is the Director for Advanced Packaging Next-Generation Products at Kulicke & Soffa Industries, Inc. Prior to joining K&S, Tom managed Wafer Level Products Business Development for STATS ChipPAC, including Fan-In and Fan-Out WLP. Before STATS ChipPAC, Tom was Vice President of Business Development at FlipChip International and responsible for the formation of FlipChip Millennium Shanghai Co. At FlipChip Technologies, Tom successfully managed the transfer of bumping technology and the startup of bump lines for all major OSATS. Tom has 20 years’ experience in technology development for wafer bumping and related Advanced Packaging technologies and extensive experience in front end semiconductor manufacturing.
Seung Wook Yoon, Ph.D., MBA, STATS ChipPAC
Dr. YOON is currently working for Products & Technology Marketing in STATS CHIPPAC LTD. His major interests are for wafer level products including eWLB/Fanout WLP, WLCSP, IPD (integrated Passive Device), flipchip bumping, TSV (Through Silicon Via), SiP and integrated 3D IC packaging. Prior to joining STATS CHIPPAC LTD, He was deputy lab director of MMC (Microsystem, Module and Components) lab, IME (Institute of Microelectronics), A*STAR (Agency of Singapore Technology and Research), Singapore. ”YOON” received Ph.D degree in Materials Science and Engineering from KAIST, Korea. He also holds MBA degree from Nanyang Business School, Singapore. He has over 200 journal papers, conference papers and trade journal papers, and over 20 US patents on microelectronic materials and electronic packaging.
Chair: Rey Alvarado, Qualcomm
Rey Alvarado who received his BSEE from MIT (Manila, Philippines) is a SC Packaging Engineer by training and is currently working with Qualcomm’s Packaging Team focusing on WLP and FOWLP Technology. Rey has more than 15 years of experience in Wafer Level Package Technology. Prior to working at Qualcomm he worked in silicon valley with Maxim Integrated for 4 years as Principal Engineer and another 7 ½ years working for Flip Chip International in Phoenix. Rey has worked experience with Texas Instruments and Johnson Matthey Electronics. He has 7 approved patents on WLP and other package interconnection processes and a dozen more that are patent pending.
Sean Chen, Magnachip
Vivek Dutta, Ph.D., Ormet Circuits Inc.
Dr. Vivek Dutta received his Ph.D. from the University of California, Berkeley. He has more than 35 years of experience in Microelectronics, Display, LED, Alternate Energy, Pharmaceutical and Metallurgical Industries. Vivek began his semiconductor career in Silicon Valley, working in Packaging & Interconnect areas at National Semiconductor. While he was the CEO of Advanpack Solutions (APS) in Singapore, Vivek introduced the pillar bump technology to the industry ~ which has become the foundation for next generation flip chip Assembly. He is currently working with Ormet Circuits, Inc. (a subsidiary of Merck KGaA) as Principal Technologist supporting the activities related to strategy, business, and technology development for back-end materials to address the next generation of microelectronics assembly needs.
Jie Gong, Ph.D., KLA-Tencor
Dr. Jie Gong received his Ph.D in Mechanical Engineering from Georgia Institute of Technology in 2016. His PhD research focuses on the non-destructive testing of solder joint quality and reliability. He has authored or co-authored several publications on various journals in the area of electronic packaging. Dr. Gong has been worked in KLA-Tencor Corporation as a Senior Application Development Engineer since 2014. His job in KLA-Tencor primarily focuses on development of state-of-art wafer inspection tool. He works very closely with front and back-end foundry customers all over the world. He has gained a lot of experience on semiconductor quality and reliability, defect inspection, semiconductor processing like wafer level packaging and TSV.
Steffen Kröhnert, NANIUM, S.A.
Dipl.-Ing. Steffen Kroehnert received his Master of Science degree in Electrical Engineering and Microsystem Technology at Technical University of Chemnitz, Germany, in 1997. Since 2009 he is Director of Technology at NANIUM S.A. in Vila do Conde, Portugal, the largest independent Semiconductor Packaging, Assembly and Test Foundry (OSAT) in Europe. Steffen is author and co-author of 23 patent filings in the area of Semiconductor Packaging Technology. He is a member of IEEE CPMT, IMAPS, MEPTEC, SMTA, VDI, VDE and GPM. He actively contributes as Co-Chair to SEMI Europe’s Advanced Packaging Conference (APC), as Technical Committee member to IEEE Electronic Components and Technology Conference (ECTC), IEEE Electronics System-Integration Technology Conference (ESTC) and IMAPS European Microelectronics Packaging Conference (EMPC), and as Assistant Technical Co-Chair (Europe) to IMAPS Device Packaging Conference and International Symposium on Microelectronics. Beginning of 2016 he became chair of the SEMI Special Interest Group ESiPAT (European SEMI integrated Packaging, Assembly and Test).
Ron Legario, Dupont
Luu Nguyen, Ph.D., Texas Instruments
Luu Nguyen is a TI Fellow at Texas Instruments, working on sensors, printed electronics, high voltage packaging, precision analog, design-for-manufacturability, and wafer level packaging. He received his Ph.D. in Mechanical Engineering from MIT, and has worked at IBM Research and Philips Research. He coedited two books on packaging, and has over 200 publications. He has over 70 patents and invention disclosures. He is a Fellow of IEEE and ASME, and a Fulbright Scholar (Finland 2002). He received two Best of Conference Awards, one Best Poster of Conference Award, and eight IMAPS and IEMT Best of Session Conference Awards. He received the 2004 IEEE CPMT Outstanding Sustained Technical Contributions Award. Other awards also include the 2003, 2014, 2015, and 2016 Mahboob Khan Outstanding Mentor Award from the Semiconductor Research Corporation in recognition of contributions to student mentoring, research collaboration, and technology transfer.
Gilles Poupon, CEA-Leti
Gilles Poupon received his formal education at University of Grenoble (France) and Conservatoire National des Arts et Métiers in Paris. He received his M.S. in Electrochemistry in 1985. He joined CEA-LETI, Grenoble, France, in 1987 where he worked for 10 years on the development of electrodeposition processes for magnetic materials on silicon thin film heads. In this theme he has published more than 10 papers and holds three patents. Since 2004, Gilles was Director of Strategic Programs on Advanced Packaging at CEA-LETI. Subsequently, he became the Manager of the High Density Interconnection and Packaging Laboratory at LETI.
Jan Vardaman, TechSearch International, Inc.
Jan Vardaman is the editor of Surface Mount Technology: Recent Japanese Developments, co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbun), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center study team involved in investigating electronics manufacturing in Asia and on the US mission to study manufacturing in China. She is a member of IEEE CPMT, IMAPS, SMTA, and SEMI. She was elected to two terms on the IEEE CPMT Board of Governors. She received her BA in Economics and Business from Mercer University in Macon, Georgia in 1979 and her MA in Economics from the University of Texas at Austin in 1981.
Chair: Shekar Krishnaswamy, Applied Materials
Shekar has over 27 years of experience in all aspects of semiconductor manufacturing including wafer fab manufacturing, assembly and test. He started his career in IBM-Fishkill working in the advanced packaging segment focused on manufacturing multi-layer ceramic packages. His specific areas of expertise include traditional Industrial Engineering methods as well as systems related methodologies such as modeling, scheduling, dispatching and factory automation. Shekar has held senior technical and management positions at IBM, Motorola and AMD including management of corporate Operations Research departments supporting factory and service groups. Shekar has a Bachelor’s degree in Mechanical Engineering and a Master’s degree in Industrial Engineering and Operations Research.
Scott Hayes, NXP Manufacturing
John Lannon, Ph.D., Micross Advanced Interconnect Technology, LLC
Dr. John Lannon is the Director of the Wafer-Level Microsystem Integration group in the Electronics and Applied Physics Division of Micross Advanced Interconnect Technology, LLC. He received his Ph.D. degree in Physics from WVU in 1996 and joined MCNC/RTI thereafter. Since 2002, he has worked with Santa Barbara Infrared, Inc. on the fabrication and improvement of resistive IR emitter devices (a MEMS-like device) for Infrared Scene Projectors (IRSP). He has also contributed to the development of WLVP for MEMS devices.
Garrett Oakes, EV Group
Garrett Oakes is the Director of Technology for EV Group North America in Tempe, Arizona. Since joining EV Group in 2006, he has held positions in Strategic Sales and Applications Engineering. In his current role, he is responsible for the day-to-day operations of the applications lab and managing the efforts of the engineering organization. Prior to EVG, he spent eleven years as a photolithography process and development engineer for IBM and Hitachi in their storage technology divisions. Garrett holds a degree in Chemical Engineering from the University of California at Davis. He also holds several U.S. patents on the subject of temporary bond and debond for back end wafer processing.