October 13-16, 2008   Wyndham Hotel   San Jose, CA     The Conference    Special Events    Tech Sessions    Workshops    Sponsors Accommodations Become a Sponsor Register Now The IWLPC is supported by Tech Sessions Featured below are 12 technical sessions, 1.5 or 2 hour programs in which three or four technical papers are presented under the direction of a chairman. Each paper is presented by the author on a topic related to the main subject of the track and is followed by audience questions. The objective of a technical session is to bring new scientific and technical developments to light. Emphasis is placed on original, previously unpublished papers. Wednesday S1 - Wafer Level Packaging Technologies, Materials and Processes S2 - 3D, Stacked, CSP, FC, SiP, SoP Materials and Processes S3 - Wafer Level Packaging Technologies, Materials and Processes S4 - 3D, Stacked, CSP, FC, SiP, SoP Materials and Processes S5 - Wafer Level Packaging Technologies, Materials and Processes S6 - 3D, Stacked, CSP, FC, SiP, SoP Materials and Processes Thursday S7 - Wafer Level Packaging Technologies, Materials and Processes S8 - 3D, Stacked, CSP, FC, SiP, SoP Materials and Processes S9 - Wafer Level Packaging Technologies, Materials and Processes S10 - 3D, Stacked, CSP, FC, SiP, SoP Materials and Processes S11 - Wafer Level Packaging Technologies, Materials and Processes S12 - 3D, Stacked, CSP, FC, SiP, SoP Materials and Processes Poster Presentations - Displayed in Registration Area during Conference High-Yield, High-Throughput Wafer Processing Using UV Laser Scribing Techniques Jeffrey P. Sercel, J.P. Sercel Associates Inc. Flash Curing of Wafer-Level Dielectric Films with VFM Robert Hubbard, Lambda Technologies Wednesday Opening Speaker- Racetrack Memory Dr. Stuart Parkin, IBM Almaden Research Center 8:15am - 9:15am Opening Panel Discussion - The Business and Marketing of WLP, ICs and Novel Devices 9:30am - 10:30am View complete details on the opening speaker and panel discussion on the Special Events page. 10:30am - 11:00am Coffee Break in Exhibit Hall Session 1 Wednesday, October 15: 11:00am - 12:30pm WLCSP: Challenges, Performance and Trends Franck Dosseul, ST Microelectronics Metal-Based Wafer-Level Packaging Dr. Shari Farrens, SUSS MicroTec A 3D-WLCSP Package Technology: Wafer Level Processing and Reliability Dr. Dan Baldwin, Engent Inc. Session 2 Wednesday, October 15: 11:00am - 12:30pm A Market & Technology Analysis of the WLP Solution for ICs, CMOS Imagers and MEMS Dr. Eric Mounier, Yole Développement Mechanical Shock Robustness of Different Wafer-Level Chip-Scale Packages (WLCSP Types) Pasi Nummila, Nokia 3D Wafer-Level Packaging Technology for CIS Applications Dr. Terrence C. Caskey, Vertical Circuits Inc. 12:30pm - 1:30pm Lunch in Exhibit Hall Session 3 Wednesday, October 15: 1:30pm - 3:00pm Vias-Last Technology for CMOS Image Sensors—Design Rules and Technology David Henry, CEA-LETI Solar Integration Takes a Page from the Semi Wafer CSP Playbook Steve Cho, Surfect Technology C4NP: Wafer Bumping & UBM More than just a Solder Ball Klaus Ruhmer, SUSS MicroTec Session 4 Wednesday, October 15: 1:30pm - 3:00pm 3D Chip Packaging For Class I Medical Devices Dr. John Dzarnoski, Starkey Laboratories Non-Destructive Method for Evaluation of Thin Wafer Edge Protection Chad Brubaker, EV Group Inc. TBD 3:00pm - 3:30pm Coffee Break in Exhibit Hall Session 5 Wednesday, October 15: 3:30pm - 5:30pm 3D Detector Activities: Wafer Bonding and Deep Reactive Ion Etch Angela Kok, SINTEF RF CMOS Circuits with Wafer-Level Packaging Inductors Hideki Hatakeyama, Tokyo Institute of Technology Lithographic Challenges and Solutions for 3D Packaging Keith Cooper, SUSS MicroTec CMOS Compatible Electroless Plating Process for Under-Bump Metallization Don Gudeczauskas, Uyemura International Corp. Session 6 Wednesday, October 15: 3:30pm - 5:30pm Ink Jet Technology Update for Flip-Chip, 3D and Wafer-Level Packaging Donald Hayes, MicroFab Technologies Inc. Metrology in Wafer-Level Microsphere Processes Jim Hisert, Indium Corporation Infrastructure Building for Embedded Die Printed Wiring Board Applications Theodore Tessier, FlipChip International A Process for Creating Hyper-Thick Polymer Cavity Packages Garrett Oakes, EV Group Inc. 5:30pm - 6:30pm Welcome Reception in Exhibit Hall Keynote Dinner Address - Wednesday, October 15: 6:30pm - 8:30pm View complete details on the Special Events page. Thursday Offshore Manufacturing Panel: Challenges and Opportunities for Semiconductor-Related Businesses and Outsourcing in China, India, Mexico and Vietnam Thursday, October 16: 8:00am - 10:00am View complete details on the Special Events page. 10:00am - 10:30am Coffee Break in Exhibit Hall Session 7 Thursday, October 16: 10:30am - 12:00pm Cost Reduction of Wafer-Level Packaging by Using Established Materials from Non-Electronics Industries Giles Humpston, Tessera Inc. NIR Imaging of Bond Integrity for Wafer-Bonding Applications Jeremy McCutcheon, Brewer Science Inc. Sapphire Wafer-Based, Wafer-Level Chip-Scale Package (WLCSP) Type LED (Light-Emitting Diode) Kwang Cheol Lee, Korea Photonics Technology Institute Session 8 Thursday, October 16: 10:30am - 12:00pm WLCSP Production Using Solder Ball Transfer Technology Andrew Strandjord, Pac Tech USA Vapor Phase vs. Convection Reflow in RoHS-Compliant Processing: A Comparative Analysis Chris Monroe, EPIC Technologies Semiconductor Packaging Solutions Utilizing Fine Powder Solder Paste Rick Lathrop, Heraeus 12:00pm - 1:00pm Lunch in Exhibit Hall Session 9 Thursday, October 16: 1:00pm - 3:00pm Application of NiPdAu Surface Finished Substrate for Chip-Scale Packaging and its Drop Test Performance Geun Sik Kim, STATS ChipPAC Thinned TSV Wafer Debonding Process Optimization Mark Privett, Brewer Science Inc. Highly Ionized Sputtering For High Aspect Ratio Through Wafer Via Metallization Juergen Weichart, OC Oerlikon Balzers Ltd. Low-Cost Compliant Wafer-Level Package (WLP) Technology Guilian Gao, Tessera Inc. Session 10 Thursday, October 16: 1:00pm - 3:00pm Non-Capillary Protection Options for WLCSPs Dr. Russell Stapleton, LORD Corporation Advanced Embedded PILR Packaging Substrate For Mobile Applications Carl Ryu, Tessera Inc. TSV Metrology: Measuring Via Depth Using Confocal Chromatic Sensor Udi Efrat, Camtek Ltd A Baseline Study on the Performance of Stencil and Screen Print Processes for Wafer Backside Coating Jeff Schake, DEK USA Inc. 3:00pm - 3:30pm Coffee Break Session 11 Thursday, October 16: 3:30pm - 5:30pm Integrated Testing & Modeling Analysis of CSPs for Enhanced Board-Level Reliability David Hays, Amkor Technology Inc. High-Rate Etching of Through Silicon Vias for Packaging Dr. Leslie M. Lea, Surface Technology Systems Innovative Front-to-Back Alignment Technology for Meeting 3D Packaging Requirements Of Leading-Edge Consumer Products Manish Ranjan, Ultratech Inc. High-Throughput Laser Tool for Drilling Vias in Silicon Terry Hannon, XSiL Session 12 Thursday, October 16: 3:30pm - 5:30pm Alternative Metallization Technologies for Flexible Circuits and Difficult to Metalize Substrates Michael Carano, OMG Electronic Chemicals Board Level Drop Test Failure Analysis of Chip-Scale Packages Nicholas Vickers, California Polytechnic State University of San Luis Obispo Use of Vectored Jets to Improve Cleaning of Micro-Array IC Packages Mike Bixenman, Kyzen Corporation Advances in Flip-Chip Die Sorting, Handling and Inspection Gerald Steinwasser, Mühlbauer Inc. Home | Top Copyright © 1999-2008 SMTA, All rights reserved. Reproduction in whole or in part without permission is prohibited. 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