Tech Sessions
Featured below are 10 technical sessions, 1.5 or 2 hour programs in which three or four technical papers are presented under the direction of a chairperson. Each paper is presented by the author on a topic related to the main subject of the track and is followed by audience questions.
The objective of a technical session is to bring new scientific and technical developments to light. Emphasis is placed on original, previously unpublished papers.
Wednesday, Nov. 7
10:30am - 12:00pm
3:30pm - 5:00pm
WLP Track
S1
S4
3D Track
S2
S5
MEMS Track
S3
S6
Thursday, Nov. 8
10:30am - 12:00pm
3:00pm – 5:00pm
WLP Track
S7
S9
3D Track
S8
S10
Wednesday, November 7, 2012
Opening Comments
Andrew Strandjord, Pac Tech USA , Conference General Chair
9:00am – 9:10am, Cedar Ballroom
Morning Plenary
Silicon Interposer: Much More than a "Piece of Silicon"
Nicolas Sillon, Ph.D., CEA-Leti
9:10am – 10:00am, Cedar Ballroom
Coffee Break
10:00am – 10:30am
Exhibit Hall, Pine/Fir/Oak Ballroom
WLP Track
Session 1 - Wafer Level Testing: Challenges and Solutions
Chair: Ted Tessier, FlipChip International
10:30am – 12:00pm, Monterey/Carmel
10:30am
Embedded Barrel Contactor – Solution for WLCSP Testing
Frank Zhou, Interconnect Devices, Inc.
11:00am
Wafer Level Testing Challenge for Flip Chip and Wafer Level Packages
Muru Yogathasan, STATS ChipPAC, Ltd. speaking on behalf of Lim Kok Hwa, STATS ChipPAC, Ltd.
11:30am
Characterization of a Novel Fluxless Surface Preparation Process for Due Interconnect Bonding
Keith Cooper, SET North America
3D Track
Session 2 - Process and Materials
Chair: Keith Cooper, SET North America
10:30am – 12:00pm, San Carlos/San Juan
10:30am
Understanding the Stacked Dies Interface Temperature and its Influence During the 3D IC Thermocompression Stacking Process
Robert Daily, IMEC
11:00am
Evaluating the Performance of Shipping Methods for Thin Silicon Wafers for 3D Stacked Applications
Richard Allen, SEMATECH
11:30am
3D Packaging- Synthetic Quartz Substrate and Interposers for High Frequency Application
Vern Stygar, AGC
MEMS Track
Session 3 - Wafer Bonding MEMS and Hermeticity Standards
Chair: Russell Shumway, Amkor Technology
10:30am – 12:00pm, Santa Clara/San Jose
10:30am
Co-Design Strategies
Mary Ann Maher, SoftMEMS
11:00am
Yield and Strength of Metal Wafer-Level MEMS Device Sealing Using Al, Au, or Ti
Kari Schjølberg-Henriksen, Ph.D., SINTEF
11:30am
Sealing Dispensing for MEMS Wafer Capping
Heakyoung Park, Nordson Asymtek
Lunch Break
12:00pm to 1:30pm
Exhibit Hall, Pine/Fir/Oak Ballroom
Panel Discussion
MEMS Integration Strategies: From A Packaging Perspective
1:30pm – 3:00pm, Cedar Ballroom
Moderators:
Roger Grace, Roger Grace Associates
Russell Shumway, Amkor Technology
Panelists:
Matthew Apanius, Desich SMART Center
Mary Ann Maher, SoftMEMS
Sean Ding, Ph.D., MEMSIC
Maik Wiemer, Ph.D.,Fraunhofer Institute
Thava Thavarajah, Fairchild Semiconductor
Coffee Break
3:00pm – 3:30pm
Exhibit Hall, Pine/Fir/Oak Ballroom
WLP Track
Session 4 - Wafer Level Packaging Materials & Process
Chair: Steven Xu, Qualcomm
3:30pm – 5:00pm, Monterey/Carmel
3:30pm
Low Stress Thick Film Photopatternable Silicones for Large Die Wafer Level Applications
Herman Meynen, Dow Corning Corporation
4:00pm
A New Single Wafer Cleaning Technology for Advanced Packaging Applications
Richard Peters, Ph.D., Dynaloy
4:30pm
Silicone and Cleaning Solvent Compatibility
Michelle Velderrain, NuSil Technology
3D Track
Session 5 - TSVs and Wafer Thinning
Chair: Peter Ramm, Fraunhofer EMFT
3:30pm – 5:00pm, San Carlos/San Juan
3:30pm
TSV Process Variations for 2.5 and 3D Semiconductor Packaging
Vern Solberg, Invensas
4:00pm
Single Sided Wet Etching for Thinning, Packaging, and Texturing Applications
Ricardo Fuentes, Matech
4:30pm
Design and Process Optimization for Competitive Through Silicon via Interposer for 3D
Cyprian Uzoh, Invensas, Inc.
MEMS Track
Session 6 - MEMS WLP, 3D Integration, and Reliability
Chair: Maaike M.V. Taklo, Ph.D., SINTEF ICT
3:30pm – 5:00pm, Santa Clara/San Jose
3:30pm
Bonding and Contacting of Vertically Integrated 3-D Microscanners
Maik Wiemer, Ph.D., Fraunhofer Institute for Electronic Nanosytems (ENAS)
4:00pm
MEMS Hermeticity and Reliability Testing Today
Mike Shillinger, Innovative Micro Technology
4:30pm
Reliability of TSV and Wafer-Level Bonding for a 3D Integrable SOI Based MEMS Application
Maaike M.V. Taklo, Ph.D., SINTEF, ICT
EXHIBITS & WELCOME RECEPTION
5:00pm – 6:00pm
Exhibit Hall, Pine/Fir/Oak Ballroom
KEYNOTE DINNER AND ADDRESS
A Trojan Chip in Your Smartphone? It's Coming...
John Ellis, bestselling author of 'Dormant Curse'
Wednesday, November 7, 2012 | 6:30pm - 8:00pm, Cedar Ballroom
Thursday, November 8, 2012
Day 2 Morning Plenary
3D Integration - A Corner Technology for Heterogeneous Integration
Paul Marchal, Ph.D., Imec
9:10am – 10:00am | Cedar Ballroom
Coffee Break
10:00 – 10:30am
Exhibit Hall, Pine/Fir/Oak Ballroom
WLP Track
Session 7 - Wafer Level Packaging Reliability
Chair: Janet Love, Interconnect Devices, Inc.
10:30am – 12:00pm, Monterey/Carmel
10:30am
Pad Lift Failure Mode Investigation for Wafer-Level Package
Laurent Gay, STMicroelectronics is not available to speak due to travel restrictions
* Paper and presentation will be available on proceedings
11:00am
Marked Reliability Increase of Plastic-Cored Solder Ball for Large Size Wafer-Level CSP
Hiroya Ishida, Sekisui Chemical Co., Ltd.
11:30am
Characterization of eWLB PoP Structures
Tom Strothmann, STATS ChipPAC, Ltd.
3D Track
Session 8 - TSVs and Lithography
Chair: Laurette Nacamulli, The Dow Chemical Company
10:30am – 12:00pm, San Carlos/San Juan
10:30am
3D TSV Micro Cu Pillar Chip-To-Substrate/Chip Assembly/Packaging Technology
Tom Strothman, Ph.D., STATS ChipPAC, Ltd
11:00am
Verification of Back-to-Front Side Alignment for Advanced Packaging
Robert Hsieh, Ph.D., Ultratech Inc.
11:30am
A Study of Coating and Developing Lithography Processes for 3Di Plating Applications
Patrick Kearney, P.E., Tokyo Electron Europe Ltd
Lunch Break
12:00pm to 1:00pm
Exhibit Hall, Pine/Fir/Oak Ballroom
Panel Discussion
3D Integration: How did we get here? Where do we need to go now?
1:00pm – 2:30pm, Cedar Ballroom
Moderator: Keith Cooper, SET North America
Panelists:
Jeff Calvert, Dow Chemical
John Lau, Ph.D., Industrial Technology Research Institute (ITRI)
David Love, Oracle
Garret Oakes, EV Group
Peter Ramm, Fraunhofer EMFT
Tom Strothmann, STATS ChipPAC
Coffee Break
2:30pm– 3:00pm
Conference Foyer
WLP Track
Session 9 - Fan-Out Wafer Level Packaging Technologies
Chair: Curtis Zwenger, Amkor Technology
3:00pm – 5:00pm, Monterey/Carmel
3:00pm
Innovative 2.5D Solution: Extended/Flip Chip eWLB (Embedded Wafer Level Ball Grid Array) Technology
Tom Strothman, STATS ChipPAC, Ltd.
3:30pm
Developments of Fan-out Wafer Level Packaging Technology for System-in-Package on Wafer-Level (WLSiP)
Jose Campos, NANIUM, S.A.
4:00pm
Adaptive Patterning for Panelized Packaging
Chris Scanlan, Deca Technologies
4:30pm
SuperPoP : a non - disruptive approach to enhancing the bandwidth & power efficiency in PoP type packages
Dev Gupta, Ph.D. , APSTL LLC
3D Track
Session 10 - 3D Materials and Debonding
Chair: Laurette Nacamulli, The Dow Chemical Company
3:00pm – 5:00pm, San Carlos/San Juan
3:00pm
Optical Profilometry of Substrate Bow Reduction Using Temporary Adhesives
John Moore, Daetec LCC
3:30pm
Wafer Spray Coating for Pre-Applied Underfill
Akira Morita, Nordson Asymtek
4:00pm
Room Temperature Debonding – An Enabling Technology for TSV and 3D Integration
Garrett Oakes, EV Group, Inc.
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