Featured below are 15 technical sessions, 1.5 or 2 hour programs in which three or four technical papers are presented under the direction of a chairperson. Each paper is presented by the author on a topic related to the main subject of the track and is followed by audience questions.
The objective of a technical session is to bring new scientific and technical developments to light. Emphasis is placed on original, previously unpublished papers.
8:30am - 9:00am
Lee Smith, Amkor Technology, IWLPC Technical Chair
Marketing Panel Discussion
9:00am - 10:30am
Moderator: Lee Smith, Amkor Technology
Panelists: E. Jan Vardaman, TechSearch International; Jean-Marc Yannou, Yole Développement; Jim Walker, Dataquest/Gartner Group
10:30am - 11:00am Coffee Break in Exhibit Hall
Session 1: WLP Track
Wednesday, October 13: 11:00am - 12:30pm
Design Optimization for Fine Pitch, Low-k and Lead-free Flip-Chip Package
Bahareh Banijamali, Tessera, Inc.
Advances in Solder Reinforcing WLCSP Coatings
Russell Stapleton, LORD Corporation
Effect of UBMs and Solders on the Electromigration Performance of WLCSP
Luu Nguyen, Ph.D., National Semiconductor Corporaton
Session 2: 3D Track
Wednesday, October 13: 11:00am - 12:30pm
Design of 3D Specific Systems
Paul Franzon, North Carolina State University
Design Methods for 3D IC Integration
Peter Schneider, Fraunhofer IZM-M
Modeling and Design for 3D TSVs
Madhaven Swamithian, E-Systems Design
Session 3: MEMS Track
Wednesday, October 13: 11:00am - 12:30pm
Metal Bonding Alternatives to Frit and Anodic Technologies for Advanced Wafer Level Packaging
Shari Farrens, Ph.D., SUSS MicroTec
The Encapsulation of MEMS/Sensors and the Realization of Molded Vias on Package Level and Wafer Level with Film Assisted Technology
Ton van Weelden, Boschman Technologies
The Development of Innovative Manufacturing Methods for 3-Dimensional Wafer Level Packaging of Ultrasonic Transducers
Jack Hoyd-Gigg Ng, Heriot-Watt University
12:30pm - 1:30pm Lunch in Exhibit Hall
Session 4: WLP Track
Wednesday, October 13: 1:30pm - 3:00pm
Cost Comparison for Flip Chip, Wire Bond, and Wafer Level Packaging
Chet Palesko, SavanSys Solutions LLC
Technology Solutions for a Dynamic and Diverse WLCSP Market
Ravi Chilukuri, Amkor Technology
High Volume Manufacturing Solution for Wafer Level Lens Molding and Stacking
KienMun Lau, EV Group
Session 5: 3D Track
Wednesday, October 13: 1:30pm - 3:00pm
Integration of Electrografted Layers for Metallization of Deep TSVs
Claudio Truzzi, Alchimer
Demonstration of Ultra-thin Si Grinding Process Controlled by in-situ Non-Contact Gauge for 3D Stacked IC (3D-SIC)
Ming Zhao, IMEC
Flip Chip Bonding: An Enabling Technology for 3DIC Integration
Keith Cooper, SET-NA
Session 6: MEMS Track
Wednesday, October 13: 1:30pm - 3:00pm
Best Known Practices for Selecting a Wafer Bonding Process
Eric Pabo, EV Group
Microspring Contacts for Integrated Test and Packaging
Eugene Chow, Palo Alto Research Center (PARC)
Miniaturized WLP for MEMS
Risto Mutikainen, VTI Technologies
3:00pm - 3:30pm Coffee Break in Exhibit Hall
Session 7: WLP Track
Wednesday, October 13: 3:30pm - 5:00pm
Evaluation of Process Limits and Design Rules for Ultra Fine Pitch Printing
Thomas Krebs, W.C.Heraeus
Scalable Interconnect Technology that Enables High Density, High Performance and Low Profile Connectivity for Board to Board, Package to Board and Board to Flex Applications
Amit Varma, High Connection Density Inc.
Wafer Bumping-The Low Cost Production Wafer Bumping Technology
Roger Gaw, Spheretek
Session 8: 3D Track
Wednesday, October 13: 3:30pm - 5:00pm
Hybrid Bonding Methods for Lower Temperature 3D Integration
Shari Farrens, Ph.D., SUSS MicroTec
Wafer Level Processing and Integration Techniques for CMOS Image Sensor Module Manufacturing
Bioh Kim, EV Group
3D Wafer Level Packaging of Micro Camera Devices
Martin Wilke, Fraunhofer IZM
Session 9: MEMS Track
Wednesday, October 13: 3:30pm - 5:00pm
A MEMS Foundry Perspective on Wafer Level Packaging
Mike Schillinger, Innovative Micro Technology
A Low Cost, High Sensitivity Magnetic Sensor, the MEMS Flux Concentrator
Alan Edelstein, U.S. Army Research Laboratory
Cost Effective Wafer Level Encapsulation for MEMS and Other Circuit Elements
Jay Mitchell, ePack, Inc.
Scaling, Packaging and System Integration, Who's Gonna Carry the Mail?
Bradley McCredie, Ph.D., IBM Fellow and Vice President, IBM Systems and Technology Group
Wednesday, October 13: 6:00pm - 8:00pm
Wafer Level Packaging...Supply and Demand
8:30am - 9:30am
Moderator: E. Jan Vardaman, TechSearch International
Panelists: Beth Keser, Qualcomm; Luu Nguyen, Ph.D., National Semiconductor; Takeshi Wakabayashi, Casio; and Matt Kaufman, Broadcom
9:30am - 10:00am Coffee Break in Exhibit Hall
Session 10: WLP Track
Thursday, October 14: 10:00am - 11:30am
Polymer Core Solder Balls as Interconnects to Enhance Board Level Reliability of WLCSPs
Luu Nguyen Ph.D., National Semiconductor Corporation
Influence of Chemistry and Process Parameters on Cu Pillar ECD for Flip Chip at 2 - 5
Richard Hollman, NEXX Systems, Inc.
Advanced Concentration/Atomic Flux Study and Reliability of Fine Pitch Lead-free Flip-Chip Package
Bahareh Banijamali, Tessera, Inc.
Session 11: 3D Track
Thursday, October 14: 10:00am - 11:30am
Depth Measurement of Through Silicon Via by using IR Confocal Microscope
Deh-Ming Shyu, Industrial Technology Research Institute (ITRI)
Mechanical Behavior Measurement of Si Wafer under Cu Plating
Po-Yi Chang, Industrial Technology Research Institute (ITRI)
Exploration of Migration and Stress Effects in POPs Considering Inhomogeneous Temperature Distribution
Kirsten Weide-Zaage , LFI Leibniz University Hannover
11:30am - 1:00pm Lunch in Exhibit Hall
Session 12: WLP Track
Thursday, October 14: 1:00pm - 2:30pm
Development of Next Generation eWLB (Embedded Wafer Level BGA) Packaging
Seung Wook Yoon, STATS ChipPAC
Wafer Level Embedded System in Package (WL-eSiP) for 3D SiP Solution
In-Soo Kang, Nepes Corporation
eWLB System in Package – Possibilities and Requirements
Thorsten Meyer, Infineon Technologies
Session 13: 3D Track
Thursday, October 14: 1:00pm - 2:30pm
Near Infrared (Nir) Prototype Optics Experiments on an Existing Macro-Defect Inspection Platform
Rolf Shervey, Rudolph Technologies, Inc.
Site-Specific Analysis of Advanced Packaging Enabled by Focused Ion Beams (FIB)
Richard Young, FEI Company
Enabling Comprehensive and Efficient Test of 3D Chips by Standardizing the Test-Access Architecture
Al Crouch, Core Instruments
2:30pm - 3:00pm Coffee Break
Session 14: WLP Track
Thursday, October 14: 3:00pm - 5:00pm
Electrical, Thermal and Mechanical Characterization of eWLB (Embedded Wafer Level BGA)
Seung Wook Yoon, STATS ChipPAC
Low Cost, High Density Chip-Layer-Vias for Chips-First Stacked Packages
James Kohl, EPIC Technologies Inc.
Embedded Active Device Packaging Technology for Real DDR2 Memory Chips
Yin-Po Hung, Industrial Technology Research Institute (ITRI)
A Laminate Based Fan-Out Embedded Die WLCSP Technology
Ted Tessier, FlipChip International
Session 15: 3D Track
Thursday, October 14: 3:00pm - 5:00pm
3D Substrate Innovation for Very Fine Pitch Flip-Chip Applications
Vern Solberg, Tessera, Inc.
Package Development of 8 Die LSOP for SSD
Ying-Long Song, Intel Asia-Pacific Research and Development
Fine Pitch 3D Dispensable Electrical Interconnects for System In Package Solutions
Jeff Leal, Vertical Circuits
Reliability Analysis of 3D Dispensable Interconnects for a System in a Package Solution
Suzette Pangrle, Vertical Circuits
