Tech Sessions
Wednesday, Nov. 7
WLP Track S1
S4
3D Track S2
S5
MEMS Track S3
S6
Thursday, Nov. 8
WLP Track S7
S9
3D Track S8
S10
Wednesday, November 7, 2012 Opening Comments
Andrew Strandjord, Pac Tech USA , Conference General ChairMorning Plenary Silicon Interposer: Much More than a "Piece of Silicon"
Nicolas Sillon, Ph.D., CEA-LetiCoffee Break
10:00am – 10:30amWLP Track
Session 1 - Wafer Level Testing: Challenges and Solutions
Chair: Ted Tessier, FlipChip InternationalEmbedded Barrel Contactor – Solution for WLCSP Testing
Frank Zhou, Interconnect Devices, Inc.
Wafer Level Testing Challenge for Flip Chip and Wafer Level Packages
Muru Yogathasan, STATS ChipPAC, Ltd. speaking on behalf of Lim Kok Hwa, STATS ChipPAC, Ltd.
Characterization of a Novel Fluxless Surface Preparation Process for Due Interconnect Bonding
Keith Cooper, SET North America
3D Track
Session 2 - Process and Materials
Chair: Keith Cooper, SET North America
Understanding the Stacked Dies Interface Temperature and its Influence During the 3D IC Thermocompression Stacking Process
Robert Daily, IMEC
Evaluating the Performance of Shipping Methods for Thin Silicon Wafers for 3D Stacked Applications
Richard Allen, SEMATECH
3D Packaging- Synthetic Quartz Substrate and Interposers for High Frequency Application
Vern Stygar, AGC
MEMS Track
Session 3 - Wafer Bonding MEMS and Hermeticity Standards
Chair: Russell Shumway, Amkor Technology
10:30am – 12:00pm, Santa Clara/San Jose
Co-Design Strategies
Mary Ann Maher, SoftMEMS
Yield and Strength of Metal Wafer-Level MEMS Device Sealing Using Al, Au, or Ti
Kari Schjølberg-Henriksen, Ph.D., SINTEF
Sealing Dispensing for MEMS Wafer Capping
Heakyoung Park, Nordson Asymtek
Lunch Break
12:00pm to 1:30pm Panel Discussion
MEMS Integration Strategies: From A Packaging Perspective
1:30pm – 3:00pm, Cedar BallroomMatthew Apanius, Desich SMART Center
Mary Ann Maher, SoftMEMS
Sean Ding, Ph.D., MEMSIC
Maik Wiemer, Ph.D.,Fraunhofer Institute
Thava Thavarajah, Fairchild Semiconductor
Coffee Break
3:00pm – 3:30pmWLP Track
Session 4 - Wafer Level Packaging Materials & Process
Chair: Steven Xu, Qualcomm
Low Stress Thick Film Photopatternable Silicones for Large Die Wafer Level Applications
Herman Meynen, Dow Corning Corporation
A New Single Wafer Cleaning Technology for Advanced Packaging Applications
Richard Peters, Ph.D., Dynaloy
Silicone and Cleaning Solvent Compatibility
Michelle Velderrain, NuSil Technology
3D Track
Session 5 - TSVs and Wafer Thinning
Chair: Peter Ramm, Fraunhofer EMFT
TSV Process Variations for 2.5 and 3D Semiconductor Packaging
Vern Solberg, Invensas
Single Sided Wet Etching for Thinning, Packaging, and Texturing Applications
Ricardo Fuentes, Matech
Design and Process Optimization for Competitive Through Silicon via Interposer for 3D
Cyprian Uzoh, Invensas, Inc.
MEMS Track
Session 6 - MEMS WLP, 3D Integration, and Reliability
Chair: Maaike M.V. Taklo, Ph.D., SINTEF ICT
Bonding and Contacting of Vertically Integrated 3-D Microscanners
Maik Wiemer, Ph.D., Fraunhofer Institute for Electronic Nanosytems (ENAS)
MEMS Hermeticity and Reliability Testing Today
Mike Shillinger, Innovative Micro Technology
Reliability of TSV and Wafer-Level Bonding for a 3D Integrable SOI Based MEMS Application
Maaike M.V. Taklo, Ph.D., SINTEF, ICT
EXHIBITS & WELCOME RECEPTION
5:00pm – 6:00pmKEYNOTE DINNER AND ADDRESS
A Trojan Chip in Your Smartphone? It's Coming... Thursday, November 8, 2012 Day 2 Morning Plenary
3D Integration - A Corner Technology for Heterogeneous Integration Coffee Break
10:00 – 10:30amWLP Track
Session 7 - Wafer Level Packaging Reliability
Chair: Janet Love, Interconnect Devices, Inc.
Pad Lift Failure Mode Investigation for Wafer-Level Package
Laurent Gay, STMicroelectronics is not available to speak due to travel restrictions
Marked Reliability Increase of Plastic-Cored Solder Ball for Large Size Wafer-Level CSP
Hiroya Ishida, Sekisui Chemical Co., Ltd.
Characterization of eWLB PoP Structures
Tom Strothmann, STATS ChipPAC, Ltd.
3D Track
Session 8 - TSVs and Lithography
Chair: Laurette Nacamulli, The Dow Chemical Company
3D TSV Micro Cu Pillar Chip-To-Substrate/Chip Assembly/Packaging Technology
Tom Strothman, Ph.D., STATS ChipPAC, Ltd
Verification of Back-to-Front Side Alignment for Advanced Packaging
Robert Hsieh, Ph.D., Ultratech Inc.
A Study of Coating and Developing Lithography Processes for 3Di Plating Applications
Patrick Kearney, P.E., Tokyo Electron Europe Ltd
Lunch Break
12:00pm to 1:00pm Panel Discussion
3D Integration: How did we get here? Where do we need to go now?
1:00pm – 2:30pm, Cedar Ballroom Jeff Calvert, Dow Chemical
John Lau, Ph.D., Industrial Technology Research Institute (ITRI)
David Love, Oracle
Garret Oakes, EV Group
Peter Ramm, Fraunhofer EMFT
Tom Strothmann, STATS ChipPAC
Coffee Break
2:30pm– 3:00pmWLP Track
Session 9 - Fan-Out Wafer Level Packaging Technologies
Chair: Curtis Zwenger, Amkor Technology
Innovative 2.5D Solution: Extended/Flip Chip eWLB (Embedded Wafer Level Ball Grid Array) Technology
Tom Strothman, STATS ChipPAC, Ltd.
Developments of Fan-out Wafer Level Packaging Technology for System-in-Package on Wafer-Level (WLSiP)
Jose Campos, NANIUM, S.A.
Adaptive Patterning for Panelized Packaging
Chris Scanlan, Deca Technologies
SuperPoP : a non - disruptive approach to enhancing the bandwidth & power efficiency in PoP type packages
Dev Gupta, Ph.D. , APSTL LLC
3D Track
Session 10 - 3D Materials and Debonding
Chair: Laurette Nacamulli, The Dow Chemical Company
Optical Profilometry of Substrate Bow Reduction Using Temporary Adhesives
John Moore, Daetec LCC
Wafer Spray Coating for Pre-Applied Underfill
Akira Morita, Nordson Asymtek
Room Temperature Debonding – An Enabling Technology for TSV and 3D Integration
Garrett Oakes, EV Group, Inc.
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International Wafer-Level Packaging Conference
