Keynote Breakfast Address
The Origins of Silicon Valley: Why and How It Happened Here
Paul Wesling, CPMT Society Distinguished Lecturer
Wednesday, November 6, 2013 | 9:00am–10:00am | Oak Ballroom
Why did Silicon Valley come into being? The story goes back to local Hams (amateur radio operators) trying to break RCA's tube patents, the sinking of the Titanic, Naval ship communications requirements, Fred Terman and Stanford University, local invention of high-power tubes (gammatron, klystron), WW II and radar, William Shockley's mother living in Palo Alto, Hetch Hetchy water, and the SF Bay Area infrastructure that developed — these factors pretty much determined that the semiconductor and IC industries would be located in the Santa Clara Valley. And since semiconductor device development and production were centered here, it made sense that Charles (Bud) Eldon of H-P would be asked by his management to start an IRE Group on Product Engineering in Palo Alto, to serve local engineers (which grew into today's CPMT Society). Bud went on to become one of IEEE's presidents.
Paul will give an exciting and colorful history of device technology development and innovation that began in San Francisco and Palo Alto, moved down the Peninsula (seeking lower costs and better housing), and ended up in the Santa Clara Valley during and following World War II. You’ll meet some of the colorful characters — Lee DeForest, Bill Eitel, Charles Litton, Fred Terman, David Packard, Bill Hewlett and others — who came to define the worldwide electronics industries through their inventions and process development.
About the Presenter
Paul Wesling has worked at GTE, Amdahl, Tandem Computers, H-P and several start-ups, in R&D, design, and manufacturing technology. Assignments included bubble memory development, IC packaging, multi-chip modules, thermal management, reliability, and executive management, as well as developing advanced technology and professional skills courses for the technical staff. A Fellow of the IEEE, he received the IEEE Centennial Medal, the CPMT Distinguished Service award, and the IEEE's Third Millennium Medal, and served as the CPMT Society's vice president of publications for 22 years. Now retired, he is communications director for the IEEE's SF Bay Area Council and the editor of the Council's GRID Magazine.
Paul, a CPMT Society Distinguished Lecturer, has served the local Santa Clara Valley CPMT chapter since 1972, as an officer and more recently as Chapter Advisor. His enthusiastic and inventive approach to volunteer organizational development was honed in the Boy Scouts, both as a youth (he's an Eagle Scout) and as a Scoutmaster of a troop of 60 to 100 Scouts for 15 years. Through his initiative and oversight, the SCV CPMT Chapter has put on over 450 multi-evening and full-day classes locally, making the chapter financially independent and setting its reputation as a high-service-delivery unit of the IEEE. The chapter earned the Society's Best Chapter award twice during his service, and has organized a number of the Society's conferences, including IEMT and SEMI-THERM.
He earned his BS-EE and his MS-Materials Science, both from Stanford University. He holds the Extra Class Ham radio callsign KM6LH. From his career in Silicon Valley, he has had a clear view of the developments here over the past 4 decades.
10th Anniversary Celebration
Hotel Restaurant—Club Maxx
Wednesday, November 6, 2013 | 5:30pm–7:00pm
Sponsored by Applied Materials
On behalf of the Technical Committee, SMTA & Chip Scale Review, we welcome everyone to the 10th Anniversary of IWLPC! Come celebrate with the speakers, conference attendees and exhibitors at the 10th Anniversary Reception. Thanks to Applied Materials for their support in sponsoring this event. Applied Materials is also recognized a Silver Sponsor. Please plan to visit their booth in the exhibit hall. The 10th Anniversary Reception is free with every registered technical conference pass and one per exhibit booth. Additional tickets will be for sale on-site. Tickets are limited!
Plenary — Metal Based MEMS Offer New Growth Opportunities
William G. Hawkins, MEMS Process Development Laboratory, General Electric Global Research Center
Wednesday, November 6, 2013 | 4:30pm–5:30pm, Oak Ballroom
Metal based MEMS have already had commercial success, the most notable example being Digital Micromirror Arrays. However, the volume of metal based MEMS remains modest in comparison with more traditional low stress poly, silicon on insulator, and “epi-poly” MEMS. This presentation will highlight the successful implementation of a new class of metal alloy MEMS, and will then discuss some features of metal alloy MEMS that enable the technology to satisfy new applications that are not yet addressed with silicon based MEMS technology.
GE's development of metal MEMS based technology will be described in the context of the microswitch application. Over an eight year period, high performance microswitches have been developed based on two different pattern electroplated metal alloys. Metal MEMS switches that are capable of switching 240 volts AC and ~10 Amps of current in a single compact chip have been demonstrated and will be discussed. These metal switches can also be fabricated on fused silica substrates, and thereby provide superior RF switching performance. The RF performance achieved will also be presented. These two microswitch examples will be used to highlight the performance advantages that have been achieved with MEMS that are fabricated from optimized plated metal alloys.
About the Presenter
Bill Hawkins has over 25 years of applied research and management experience in inkjet, microelectronics and MEMS technology. Bill was a member of a small team of researchers that initiated and matured Xerox’s thermal inkjet technology, first in Corporate Research and then in the Inkjet Business Division. Xerox inkjet revenues grew to over $1 B. Bill holds 51 patents in various aspects of inkjet technology. Bill then became VP and Chief Operating Officer at Infotonics Technology Center in 2002. Infotonics (now STC) is a not-for-profit Research Center that constructed and now maintains a micro-fabrication facility where member companies and other businesses can carry out MEMS R&D. Bill joined GE’s Global Research Center (GRC) in 2005. Bill manages a department within GRC’s Micro and Nano Structures and Technology (MNST) organization. MNST develops specialized electronic components that enable new levels of product performance and new product features for GE products. The organization has expertise in device and process design, fabrication, test, packaging and applications engineering, as well as collaborative research with a metallurgy R&D organization at the Research Center and with universities.
Plenary - A Consumer Driven Market - This Changes Everything
Simon McElrea, Invensas Corporation
Thursday, November 7, 2013 | 9:00am - 10:00am, Oak Ballroom
With the dawning of “Generation Mobile” comes a whole new landscape in microelectronics manufacturing. Consumers are more educated about what makes their mobile devices tick and are in the driver's seat for what they want to see next in terms of functionality. What’s more, these devices are no longer viewed as luxury items, but rather as necessities for daily living. Then add advancements in interconnect technologies for logic, memory, sensors and more, which have the ability to make every technogeek’s dream a reality. So what is the fly in the ointment? Cost of manufacturing and time to market. The traditional semiconductor manufacturing model is antiquated, stuck in the PC era, and can’t keep pace with savvy consumer demand. This talk will address these issues and offer insight into what might be needed to inspire change in the ecosystem and infrastructure.
About the Presenter
Simon McElrea, President of Invensas Corporation, is an industry advocate promoting the need for supply chain collaboration as "advanced packaging" is increasingly displaced by interconnect technology. He has more than 15 years of executive, technical and operational management experience in semiconductor and green technology businesses, holding senior positions at Tessera, Honeywell Electronic Materials, Amkor Technology, Vertical Circuits and Johnson Matthey PLC. He has authored numerous patents in advanced electronics.
Panel Discussion 3D High Volume Manufacturing — Are We There Yet?
Thursday, November 7, 2013 | 1:30pm–3:00pm, Oak Ballroom
Hosted by Invensas Corporation
When is a product or a technology deemed to be in HVM? It has been several years since the first stacked memory (Flash, DRAM) products were announced. Since then, various parts of the industry's supply chain have steadily geared up for 3D products. This panel will examine the factors that signal the transition of a technology into High Volume Manufacturing and how close we are to achieving it in 3D.
Moderator: Sitaram Arkalgud, Ph.D., Invensas Corporation
Laura Rothman Mauer, Solid State Equipment LLC.
Dr. Suresh Ramalingam, Xilinx
Jim Walker, Gartner Technology
Abe Yee, NVIDIA Corporation
Sitaram Arkalgud, Ph.D., is Vice President of 3D Technology at Invensas Corporation, a complete Interconnectology solutions provider for advanced mobile applications. Previously, Arkalgud started and led 3D IC development at SEMATECH, where the focus was on delivering manufacturable process technologies for 3D interconnects. In addition, he has worked in a variety of roles spanning R&D and manufacturing in memory and logic technologies at Infineon/Qimonda and Motorola. Arkalgud holds a doctorate and master’s degree in materials engineering from Rensselaer Polytechnic Institute in Troy, NY, and a bachelor’s degree in metallurgical engineering from Karnataka Regional Engineering College, Suratkal, India. He is the author of several publications and holds 14 U.S. patents.
Jim Walker is Research Vice President of the Semiconductor Manufacturing and Emerging Technologies Group of Gartner (NYSE- IT). Some of his previous business experiences include founder and co-owner of EM2, a semiconductor subcontract packaging and assembly manufacturing company, and marketing manager at National Semiconductor, where he was responsible for licensing the company’s proprietary manufacturing technology. Jim has served on the advisory boards of Bridgewave Communications, Inc., Surfect Technologies, the Microelectronic Packaging and Test Engineering Council (MEPTEC), and the Surface Mount Technology Association (SMTA). His educational background includes a B.S. in Chemistry from California State Polytechnic University and post-graduate work in at California State University at Los Angeles with focus on business and education.
Abe Yee is currently Sr. Director of Advanced Technology and Package Development at NVIDIA Corporation. His current responsibilities include pathfinding and benchmarking technologies, investigating new technologies and setting NVIDIA's packaging roadmap for both GPU and Mobile products. From 2000-2002 he was Director of Engineering at SUN Microsystems responsible for SPARC processor manufacturing and reliability. He served as VP of Operations at Equator Technologies from 1996-2000 responsible for all aspects of development, NPI and production with manufacturing partners. From 1983-1996 he was at LSI Logic Corp, where he held various senior management roles in technology development and operations. Dr. Yee received his BA in Mathematics and Physics and his MA and PhD in Physics from UC Berkeley.
Laura Rothman Mauer is the Chief Technical Officer at Solid State Equipment LLC. Laura brings over 35 years of semiconductor experience working on a broad range of technical areas including semiconductor and packaging process development, reliability engineering, contamination control, environmental technologies and knowledge management. Extensive experience at IBM as a Program Manager, at SC Fluids as CTO and at Brewer Science as Director of R&D.
Dr. Suresh Ramalingam graduated in 1994 with a Ph.D. in Chemical Engineering from Massachusetts Institute of Technology, Cambridge. He holds 13 US Patents, Ross Freeman Award for Technical Innovation and ECTC 2011 Best Paper Awards. He started his career at Intel developing Organic Flip Chip Technology for Micro-processors. As Senior Director of Advanced Packaging he currently manages Package Design and Technology Development including TSV/3D for Xilinx FPGA products.