The European 3D Technology Platform for Heterogeneous Systems
Peter Ramm, Fraunhofer IZM-M
Tuesday, October 12, 5:00pm – 6:30pm
The presentation will begin at 5:30pm.
As predicted by the ITRS roadmap, semiconductor industry development dominated by shrinking transistor gate dimensions alone will not be able to overcome the performance and cost problems of future IC fabrication. Today 3D integration based on through silicon vias (TSV) is a well-accepted approach to overcome the performance bottleneck and simultaneously shrink the form factor. Several full 3D process flows have been demonstrated, however there are still no microelectronic products based on 3D TSV technologies in the market - except CMOS image sensors. In addition to the enabling of further improvement of transistor integration densities, 3D integration is a key technology for integration of heterogeneous technologies. Miniaturized MEMS/IC products represent a typical example for such heterogeneous systems demanding for smart system integration rather than extremely high transistor integration densities. The European 3D technology platform that has been established within the EC funded e-CUBES project is focusing on the requirements coming from heterogeneous systems. Click here to view the full description
Marketing Panel Discussion
Wednesday, October 13: 9:00am - 10:30am Moderator: Lee Smith, Amkor Technology Panel members include:
Jim Walker, Dataquest/Gartner Group
Jan Vardaman, TechSearch International
Jean-Marc Yannou, Yole Développement
An all-star panel featuring three of the semiconductor industry's most respected forecasters is scheduled for Wednesday morning. Panelists will participate in a lively discussion moderated by Lee Smith of Amkor Technology.
The panel is free to all conference registrants and exhibitors, and includes individual presentations as well as a question-and-answer period.
Keynote Dinner Address
Scaling, Packaging and System Integration, Who's Gonna Carry the Mail?
Bradley McCredie, Ph.D., IBM Fellow and Vice President, IBM Systems and Technology Group
Wednesday, October 13, 6:30pm – 8:00pm
The keynote dinner is included with all paid registrations for the Conference and with each tabletop exhibitor registration.
Our industry continues to look for designs and technologies that what will continue to generate value for future systems. We continue to watch the returns from ever increasing investments in technology scaling yield less and less. It is not likely that any single design or technology discipline will carry the mail like Si technology scaling has for so many years. This talk will take a short survey of this problem and explore areas where we might find some answers.
Dr. McCredie received his BS, MS, and PhD in electrical and computer engineering from the University of Illinois in 1985, 1987 and 1991, respectively. His primary interests were electromagnetic modeling and simulation. He then joined IBM and continued his work in packaging focused on IBM’s mainframe systems. In 1996 he began working on POWER based systems. His first assignment was on POWER3. He delivered the cache subsystem design and packaging.
Dr. McCredie became one of the lead architects of IBM’s POWER4 systems and chip and went on to become the POWER4 system chief engineer and delivered that system in 2001. The POWER4 systems propelled IBM from a trailing position as the #3 Unix system provider in the industry to its current position as the #1 Unix systems supplier.
After delivering the POWER4 systems, Dr. McCredie led the design and delivery of the POWER6 processor for IBM. POWER6 is the highest frequency processor in the industry and is the only processor in the industry to earn a #1 benchmark result in all of the major benchmarks including SPEC, TPC-C, SAP and Java. He then focused on POWER7 systems.
After leading the chip design team for over six years, he has taken on the system executive role for POWER7. His responsibilities included delivery of all system components including hardware and software elements. In 2004 Dr. McCredie was appointed to the position of IBM Fellow, IBM’s highest technical position; then in 2009 he was appointed to the position of IBM Vice President and Fellow and is now leading all POWER chip development for IBM systems.
Supply Chain Panel Discussion
Wafer Level Packaging... Supply and Demand
Thursday, October 14, 8:30am - 9:30am
The final day of the conference will lead off with an executive panel assembled from a number of the leading electronics companies from around the world, to discuss the latest Supply and Demand issues related to Wafer Level Packaging. The panel members represent a broad viewpoint from within in the industry, including: semiconductor manufacturing, backend manufacturing, end users, and business analysts. The panel will also be soliciting questions from the audience. This is a great opportunity to get current analysis and future perspectives on the latest technology and markets for wafer level packaging.
The panel moderator is Jan Vardaman, TechSearch International. The panel members include Beth Keser, Qualcomm, Luu Nguyen, Ph.D., National Semiconductor; Takeshi Wakabayashi, Casio; and Matt Kaufman, Broadcom. These participants know the ins and outs of WLCSPs. It’s a great opportunity to get “insider” tips that will launch or improve your WLCSP endeavors.
