October 22 - 24, 2019
DoubleTree by Hilton San Jose
San Jose, California, USA

Panel Discussion



Wednesday, October 24


Tanja Braun Jan Vardaman

What is the Sweet Spot for Large Area (Panel) Packaging?


Moderators:
Tanja Braun, Fraunhofer IZM
E. Jan Vardaman, TechSearch International, Inc.

Panelists:
  • Richard Bae, Samsung Electro-Mechanics Company (SEMCO)
  • Thomas DeBonis, Intel
  • John Hunt, ASE
  • Markus Leitgeb, AT&S
  • Tim Olson, Deca Technologies


  • Fan-out Wafer Level Packaging has found widespread use in applications ranging from automotive and high-performance systems to mobile and consumer applications. A multitude of formats have been developed and moved into production. As with any package format, there is a quest for lower cost, and FO-WLP is no exception. Panel-level options are measured against wafer-level packaging and yield achievements. Until now the sweet spot for PLP is not really defined concerning target applications, integration density, panel size, lines and spaces, number of layers and yield. The topic on the sweet spot for PLP will be discussed with key players from industry.





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    Organized by: SMTA and ChipScale Review



    Supported by:
    IEEE Electronic Packaging Society Panel Level Packaging Consortium

    Supporting Media:
    MEPTEC Open Sky Communications