October 23 - 25, 2018
DoubleTree by Hilton San Jose
San Jose, California, USA

Panel Discussion

Tuesday, October 24

Ira Feldman Jan Vardaman

Scaling-Up Panel Level Processing: Challenges and Opportunities

E. Jan Vardaman, TechSearch International, Inc.
Ira Feldman, Feldman Engineering Corp.

  • Timothy Kryman, Rudolph Technology
  • T.H. Kim, nepes Corporation
  • Kazuo Yasuda, SCREEN
  • Tanja Braun, Ph.D., Fraunhofer IZM
  • Michael Frazier, Xcerra Corporation

  • Economics continues to drive packaging and assembly choices, and fan-out wafer level packaging (FO-WLP) is no exception. The semiconductor industry has traditionally increased the production size of the panel or wafer to reduce the cost per unit. Silicon has grown over time from 50 mm to 300 mm wafers. PCB fabrication has increased the overall size of a panel to produce more PCBs per panel. Similarly 10th generation LCD panels have grown to almost 10 m2. Packaging and test is no exception and a number of companies are promoting moving from single device and wafer level packaging to panel level processing (PLP) to reduce costs.

    What are the challenges to the adoption of PLP? Is there sufficient unit demand and will the economics justify the adoption? What are some of the technology barriers? How will packages be tested? Are their new inspection requirements for large area formats? What standards are required?

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    Organized by: SMTA and ChipScale Review

    Supported by:
    MEMS Journal MEPTEC MCA Public Relations