Tuesday, October 24, 2017 | 11:00am
The Next Step in Moore's Law: Getting Rid of the Package and Replacing the Printed Circuit Board
Subramanian Iyer, Ph.D.Distinguished Chancellor's Professor
Center for Heterogeneous Integration and Performance Scaling (CHIPS), Henry Samueli School of Engineering and Applied Science
University of California, Los Angeles
Silicon features have scaled by over 1500X for over six decades, and with the adoption of innovative materials delivered better power-performance, density and till recently, cost per function, almost every generation. This has spawned a vibrant system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. The integration of multiple dies on packages and boards has, however, scaled only modestly by a factor of three to five times. However, as SoCs have become bigger and more complex, the Non-Recurring Engineering (NRE) Charge and time to market have both ballooned out of control leading to ever increasing market consolidation. We need to address this problem through novel methods of system Integration. With the well-documented slowing down of scaling and the advent of the Internet of Things, there is a focus on heterogeneous integration and system-level scaling. Packaging itself is undergoing a transformation that focuses on overall system performance through integration rather than on packaging individual components. We propose ways in which this transformation can evolve to provide a significant value at the system level while providing a significantly lower barrier to entry compared with a chip-based SoC approach that is currently used. More importantly it will allow us to re-architect systems in a very significant way. This transformation is already under way with 3-D stacking of dies, Wafer level fan-out processing, and will evolve to make heterogeneous integration the backbone of a new SoC methodology, extending to integrate entire Systems on Wafers (SoWs). We will describe the technology we use and the results to-date. This has implications in redefining the memory hierarchy in conventional systems and in neuromorphic systems. We extend these concepts to flexible and biocompatible electronics with medical engineering applications and what we call truly three dimensional systems.
Subramanian S. Iyer (Subu) is Distinguished Chancellor’s Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department at the University of California at Los Angeles and is Director of the Center for Heterogeneous Integration and Performance Scaling ([Chips.ucla.edu]CHIPS). He obtained his B.Tech. from IIT-Bombay, and Ph.D. from UCLA and joined the IBM T.J. Watson Research Center at Yorktown heights, NY and later moved to the IBM Systems and Technology Group at Hopewell Junction, NY where he was appointed IBM Fellow Till 2015 he was Director of the Systems Scaling Technology Department. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical Fuses, embedded DRAM and 45nm technology used at IBM and IBM’s development partners to make the first generation of truly low power portable devices like the iPhone. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. He has published over 300 papers and holds over 70 patents. His current technical interests and work lie in the area of advanced packaging and three-dimensional integration for system-level scaling and new integration and computing paradigms as well as the long-term semiconductor and packaging roadmap for logic, memory and other devices including hardware security and supply-chain integrity. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow, an APS Fellow and a Distinguished Lecturer of the IEEE EDS as well as its treasurer. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012. He also studies Sanskrit in his spare time.
Wednesday, October 25, 2017 | 8:30am
Richard (Kwang Wook) BaeVice President, Corporate Strategy & Planning
Innovation and economics in semiconductor fabrication have followed Moore’s Law in past decades. However, as front-end processing is facing physical limits and the economic advantage described by Moore’s Law is fading, innovation in back-end processing has become critical. As the industry moves “Beyond Moore,” two questions come to mind: 1) What is the next-generation of packaging, and 2) What features should it have? Related to these topics are a discussion of the characteristics of the fan-out business, and the advantage of Samsung’s fan-out panel-level packaging (FOPLP).
Richard (Kwang Wook) Bae is currently Vice President of Samsung Electro-Mechanics and Head of the Corporate Strategy & Planning Team. He received his Master of Material Science & Engineering from Hanyang University in 1991. Bae then became Senior Researcher of SEMCO. In 2003 received his US CPA & Practice license and in 2004 he received his MBA from KAIST - Korea Advanced Institute of Science and Technology. In 2004 he became the Head of Technology Management Group at Samsung Electro-Mechanics and in 2008 the Head of US R&D. By the end of 2012 he was the VP, Head of Marketing of Global Marketing Division and in 2014 advanced to his current role.
Wednesday, October 25, 2017 | 1:00pm
Innovative Packaging Technologies
Usher in a New Era for Integration Solutions
Dr. Han Byung JoonChairman
Rapidly evolving demands for greater system performance, increased functionality and reduced form factor are driving three key paradigm shifts in the industry. First, product miniaturization and the modularization of functionality is accelerating growth in system level integration. Second, increasing I/O densities and complex integration requirements in a smaller form factor are leading to a wide range of 2.5D and 3D fan-out wafer level packaging solutions. Third, Chinese fabless customers are requiring sophisticated packaging technologies to be competitive with the top international players. Dr. Han will discuss these important paradigm shifts and how wafer level technology is a key enabler for innovative integration solutions in smartphones, Internet of Things and wearable devices, data storage, networking and automotive electronics.
Dr. BJ Han is currently the Group Chairman of the Technology Strategy Committee overseeing technology direction and execution of the JCET group of companies. He joined STATS ChipPAC in 1999 as Chief Technology Officer and went on to become the company’s Chief Executive Officer in 2015 before becoming Group Chairman in 2017. Prior to joining STATS ChipPAC, he worked for 14 years at AT&T Bell Laboratories, IBM Research and Anam Semiconductor. Dr. Han received his PhD from Columbia University in the city of New York and completed The Advanced Management Program (AMP) at Harvard Business School.