The Next Step in Moore's Law: Getting Rid of the Package and Replacing the Printed Circuit Board
Subramanian Iyer, Ph.D.Distinguished Chancellor's Professor
Center for Heterogeneous Integration and Performance Scaling (CHIPS), Henry Samueli School of Engineering and Applied Science
University of California, Los Angeles
Silicon features have scaled by over 1500X for over six decades, and with the adoption of innovative materials delivered better power-performance, density and till recently, cost per function, almost every generation. This has spawned a vibrant system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. The integration of multiple dies on packages and boards has, however, scaled only modestly by a factor of three to five times. However, as SoCs have become bigger and more complex, the Non-Recurring Engineering (NRE) Charge and time to market have both ballooned out of control leading to ever increasing market consolidation. We need to address this problem through novel methods of system Integration. With the well-documented slowing down of scaling and the advent of the Internet of Things, there is a focus on heterogeneous integration and system-level scaling. Packaging itself is undergoing a transformation that focuses on overall system performance through integration rather than on packaging individual components. We propose ways in which this transformation can evolve to provide a significant value at the system level while providing a significantly lower barrier to entry compared with a chip-based SoC approach that is currently used. More importantly it will allow us to re-architect systems in a very significant way. This transformation is already under way with 3-D stacking of dies, Wafer level fan-out processing, and will evolve to make heterogeneous integration the backbone of a new SoC methodology, extending to integrate entire Systems on Wafers (SoWs). We will describe the technology we use and the results to-date. This has implications in redefining the memory hierarchy in conventional systems and in neuromorphic systems. We extend these concepts to flexible and biocompatible electronics with medical engineering applications and what we call truly three dimensional systems.
Richard (Kwang Wook) BaeVice President, Corporate Strategy & Planning
Innovation and economics in semiconductor fabrication have followed Moore’s Law in past decades. However, as front-end processing is facing physical limits and the economic advantage described by Moore’s Law is fading, innovation in back-end processing has become critical. As the industry moves “Beyond Moore,” two questions come to mind: 1) What is the next-generation of packaging, and 2) What features should it have? Related to these topics are a discussion of the characteristics of the fan-out business, and the advantage of Samsung’s fan-out panel-level packaging (FOPLP).
Innovative Packaging Technologies
Usher in a New Era for Integration Solutions
Han Byung Joon, Ph.D.Chief Executive Officer
Rapidly evolving demands for greater system performance, increased functionality and reduced form factor are driving three key paradigm shifts in the industry. First, product miniaturization and the modularization of functionality is accelerating growth in system level integration. Second, increasing I/O densities and complex integration requirements in a smaller form factor are leading to a wide range of 2.5D and 3D fan-out wafer level packaging solutions. Third, Chinese fabless customers are requiring sophisticated packaging technologies to be competitive with the top international players. Dr. Han will discuss these important paradigm shifts and how wafer level technology is a key enabler for innovative integration solutions in smartphones, Internet of Things and wearable devices, data storage, networking and automotive electronics.