Advanced Packaging in the New Connected World
October 22 - 24, 2019
DoubleTree by Hilton San Jose
San Jose, California, USA

Keynote Presenters

Tuesday, October 23, 2018 | 9:00am
Douglas C.H. Yu, Ph.D

Growth of WLSI and Wafer Foundry with Moore's Law and More-than-Moore, and Vice Versa

Douglas C.H. Yu, Ph.D.

Vice President, Research & Development
Taiwan Semiconductor Manufacturing Company (TSMC)

WLSI (Wafer Level System Integration) is a disruptive packaging technology platform that employees a round wafer as an integration substrate, as contrast to conventional panel substrate approach, to enable high density, high performance system integration. The integrated components include chip, cubes and pre-formed package of flexible sizes, for wide applications from IoT, mobile, to edge and cloud computing. It drove recent explosion of AI/machine learning wave by enabling high computing power along with high bandwidth communication. Effective and efficient chiplet integration with WLSI also helps to sustain Moore’s Law. At the same time, we grow from an IC- to (sub)-system integration wafer foundry. In this talk, we present the new developments that further enhance system performance, power, and density for the growth of WLSI and wafer foundry, enabling and being enabled by the growth of Moore’s Law and More-Than-Moore

Douglas C.H. Yu is a Vice President of TSMC R&D in charge of advanced interconnect and packaging technology development. He pioneered and delivered WLSI (Wafer-Level-System-Integration) technology platform, which includes 3DIC/TSV (CoWoS®), Integrated Fan Out Wafer-Level-Packaging (InFO) and advanced WL-CSP, for system integration of wide range products. Prior to that, Doug was responsible for the development and of industry’s first advanced on-chip Cu/Low-K interconnects at TSMC’s 0.13 micron technology node. He received Ph.D. degree on Materials Science and Technology from Georgia Institute of Technology. He has numerous publications and granted more than 500 US patents. Doug is an IEEE Fellow.

Tuesday, October 23, 2018 | 1:45pm
Walden Rhines, Ph.D.

Monolithic versus Heterogeneous Packaging: Where Does the Future Lie?

Walden Rhines, Ph.D.

President and Chief Executive Officer
Mentor, a Siemens business

Cost, risk, and the limitations of monolithic scaling are driving the growth of multi-die (heterogeneous) advanced IC packaging solutions. The integration of different functions into a highly optimized, yet variant-capable device is attractive to markets such as automotive, industrial IoT, and aerospace & defense, whose applications often do not have the quantities to justify the cost of a SoC implementation. Although system-in-package (SiP) has been around for some years and is well proven, the advent of high-density advanced packaging (HDAP) designs has stimulated the development of new tools and processes that can address such verification challenges as overall device connectivity, timing, functional verification, and thermal/stress analysis.

Wednesday, October 24, 2018 | 9:00am
Veer Dhandapani, Ph.D.

Interconnected World and the Automotive Paradigm

Veer Dhandapani, Ph.D.

Head of Automotive Packaging
NXP Semiconductors

Innovations in the automotive industry today are synonymous with technological advances not only in automotive domains such as electric power, braking etc. but also in mobile, home, office electronics and their applications to the automobiles we drive. Energy efficiency, the seamless connected car and advanced driver assist systems are the dominant trends driving the integration of highly innovative electronics in cars. This presentation will discuss how these technologies merge to serve the pilots of these advanced machines and the unique challenges that unifying these diverse domains provide. Meeting reliability, vehicle and functional safety as well as security requirements that the above trends dictate will be the focus of this presentation. These challenges are constantly evolving, especially as automotive electronics take advantage of the benefits of silicon scaling and incorporate leading edge nodes earlier than ever before.

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Organized by: SMTA and ChipScale Review

Supported by:
IEEE Electronic Packaging Society Panel Level Packaging Consortium

Supporting Media:
MEPTEC Open Sky Communications