October 22 - 24, 2019
DoubleTree by Hilton San Jose
San Jose, California, USA

Highlights of the 14th Annual IWLPC!

Silicon to Systems

October 24 - 26, 2017 | San Jose, CA

The 2017 14th Annual International Wafer-Level Packaging Conference has once again set an attendance record. Each year, IWLPC sets the stage in the heart of Silicon Valley, providing attendees with the opportunity to network and attend presentations by industry experts. IWLPC is a highly regarded technical conference that covers leading edge advancements in wafer-level packaging. With this year's theme, "Silicon to Systems," the program tracks comprised WLP/FOWLP, 2.5D/3D, and Advanced Manufacturing and Test.

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Pertinent statistics from this year's show include:

  • 880 Total Attendees
  • 68 Exhibiting Companies
  • 16 Countries Represented
  • 48 Technical Papers

    Three leading industry experts were the keynote presenters. Subramanian Iyer, Ph.D., Distinguished Chancellors Professor, University of California, Los Angeles, presented his talk entitled, "The Next Step in Moore's Law: Getting Rid of the Package and Replacing the Printed Circuit Board." Richard (Kwang Wook) Bae, VP, Corporate Strategy & Planning, Samsung Electro-Mechanics, discussed "Samsung's FOPLP: Beyond Moore." Han Byung Joon, Ph.D., Group Chairman of the Technology Strategy Committee, JCET, presented: "Innovative Packaging Technologies Usher in a New Era for Integration Solutions."

    The targeted panel discussion, "Scaling-Up Panel Level Processing: Challenges and Opportunities," was moderated by Jan Vardaman of TechSearch International, and Ira Feldman of Feldman Engineering. This engaging panel comprised Timothy Kryman/Rudolph Technologies, T.H. Kim/nepes Corporation, Kazuo Yasuda/SCREEN Semiconductor Solutions, Tanja Braun Ph.D./Fraunhofer IZM, and Michael Frazier/Xcerra Corporation.

    The final day was dedicated to multiple workshops with topics that enhanced and broadened everyone's portfolio. The two-day expo showcased a wide array of new products and services from companies serving the semiconductor packaging industry. The exhibition booths and tabletops sold out weeks ahead of the conference—a good indication that the expo floor was the place to network.

    Mark your calendar for the 15th Annual IWLPC, which will take place October 23-25, 2018. The technical committee is accepting interested experts who wish to join it. Abstract submissions will be open through April 10, 2018.

    Best Presentation & Papers Awards Announced


    The IWLPC Technical Committee is pleased to announce the Best of Conference, Best Presentation & Best Papers in WLP, 3D, Advanced Manufacturing and Test tracks as chosen by the technical committee and attendees based on technical merit, relevance, originality, knowledge of subject, quality of material, and quality of presentation.

    Best of Conference Presentation - Guilian Gao, Ph.D., XPERI/Invensas
    "Development of Hybrid Bond Interconnect Technology for Die-To-Wafer and Die-to-Die Applications"

    Best of Conference Paper - Wolfram Steller, Ph.D., Fraunhofer IZM ASSID
    "Dual Side Chip Cooling Realized by Microfluidic Interposer Processing on 300mm Wafer Diameter"

    Best of 3D Track Paper - Wolfram Steller, Ph.D., Fraunhofer IZM ASSID
    "Dual Side Chip Cooling Realized by Microfluidic Interposer Processing on 300mm Wafer Diameter"

    Best of WLP Track Paper - Tanja Braun, Ph.D., Fraunhofer IZM
    "Fan-Out Wafer and Panel Level Technology for Advanced LED Packaging"

    Best of Advanced Manufacturing and Test Track Paper - Paul Werbaneth, Intevac, Inc.
    "Process and Productivity Results from a Carrier-Based Linear Transport PVD Systems for RDL Seed Layer Deposition in Fan-Out Packaging Applications"

    Purchase the proceedings here!




    Photos from IWLPC 2017





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    Organized by: SMTA and ChipScale Review



    Supported by:
    IEEE Electronic Packaging Society Panel Level Packaging Consortium

    Supporting Media:
    MEPTEC Open Sky Communications