Highlights of the 13th Annual IWLPC!
Bridging the Interconnect Gap
October 18 - 20, 2016 | San Jose, CA
The 13th International Wafer-Level Packaging Conference (IWLPC) and Exhibition, held in Silicon Valley on October 18-20, offered an excellent insight into current issues and future challenges in advanced packaging technologies. An impressive array of 48 presentations, five interactive presentations (poster sessions), and four workshops covered a wide array of topics with focus on various aspects of fan-out wafer-level packaging (FOWLP), 3D packaging and manufacturing, and microelectromechanical systems (MEMS). Overall, attendance was higher than what I’ve seen in past years, and the expo hall was sold out completely. Table-top exhibitors, who couldn’t get space inside the main exhibition hall, lined up their display items along the walkways in front of the main exhibit area. Quite fittingly, the main theme of the conference was "Bridging the Interconnect Gap," thus highlighting one of the major challenges our industry is facing as "big data" seeps into our daily lives in multiple forms at the workplace, home, and in between.
A highly regarded annual technical conference that covers leading edge advancements in the area of Wafer-level technologies, the 2016 IWLPC conference was a great success with more 788 attendees. Three major themes were woven into the technical sessions: 1) Fan-out WLCSP, 2) 2.5 and 3D IC packaging, 3) MEMS packaging and a newly formed Manufacturing sub-track.
View the Technical Program for details.
Here are some of the conference and expo highlights:
Each year, IWLPC's venue in the heart of Silicon Valley also provides attendees with a great opportunity to network and meet with industry experts. We look forward to another successful conference next year and are actively looking for interested experts to participate in the technical committees. It is our key contributors who maintain the high technical quality of the presentations with which IWLPC has become synonymous.