Bridging the Interconnect Gap
October 24 - 26, 2017
DoubleTree by Hilton San Jose
San Jose, California, USA

Highlights of the 12th Annual IWLPC!

Interconnecting WLP, MEMS & 2.5/3D Integration

October 12-14, 2015 | San Jose, CA

A highly regarded annual technical conference that covers leading edge advancements in the area of wafer-level technologies, the 2015 IWLPC conference was a great success with more than 650 attendees. Three themes were woven into the technical sessions: 1) fan-out WLCSP, 2) 2.5 and 3D IC packaging, and 3) MEMS packaging. The panel discussions and plenary presentations provided an effective backdrop to mingle and discuss these topics with a broad range of industry experts working in these areas. In particular, the targeted panel discussions chaired by Jan Vardaman on large-panel fan-out processing, and Francoise von Trapp on 2.5 and 3D technologies, provided a comprehensive perspective and highlighted how both processes are vying for next-generation advanced packaging applications.

View the Conference brochure (PDF) for details.

Here are some of the conference and expo highlights:

  • 650 attendees
  • 65 exhibiting companies with 195 booth staff in attendance
  • 16 countries represented
  • 43 technical papers
  • Each year, IWLPC's venue in the heart of Silicon Valley also provides attendees with a great opportunity to network and meet with industry experts. We look forward to another successful conference next year and are actively looking for interested experts to participate in the technical committees. Each year, it is our key contributors who maintain the high technical quality of the presentations with which IWLPC has become synonymous.

    Photos from IWLPC 2015





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    Organized by: SMTA and ChipScale Review



    Supported by:
    MEMS Journal MEPTEC