October 23 - 25, 2018
DoubleTree by Hilton San Jose
San Jose, California, USA

NEW! Interactive Presentations (Posters)

Tuesday, October 24


Stop by and learn current research, case histories and projects from authors through Interactive Presentations. Interact with authors directly on topics on 3D, Wafer-Level Packaging, Advanced Manufacturing & Test.

Presentation will include:

Interconnect Reuse Resolution and Verification with Bum Compensation for HDAP Designs
Zain Ali, Mentor Graphics

3D Wafer Level Compression Molding Technology Development For CMOS Image Sensor
Tony Curtis, FCI- Huatian Technologies

Plasma Polymerization Applications for Advanced Wafer Level Packaging
Abe Ghanbari, Ph.D., Semblant

Low Temperature Multilayer EMI Shielding
Andreas Erhart, Evatec AG

Application of Picosecond Ultrasonics for Advanced Packaging Process Monitoring and Control
Priya Mukundhan, Rudolph Technologies

Full Wafer Redistribution and Embedding as Key Technology for a Multi-Scale Neuromorphic Hardware Cluster
Kai Zoschke, Fraunhofer IZM

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Organized by: SMTA and ChipScale Review

Supported by:
MEMS Journal MEPTEC MCA Public Relations