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Chips Down? - Wafers Up! - IWLPC
The IWLPC is
supported by 
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International Wafer-Level Packaging Conference
October 27-30, 2009
New Venue!
The Santa Clara Marriott, located in the heart of Silicon Valley, minutes from Norman Y. Mineta San Jose International Airport and only 45 minutes from San Francisco, will be the new setting for IWLPC.
Sponsored jointly by the SMTA and
Chip Scale Review magazine, the annual IWLPC explores cutting edge topics in wafer-level packaging and IC/MEMS/MOEMS packaging, including 3D/Stacked/CSP/SiP/SoP and mixed technology packages.
Keynote Speaker Announced
Dr. Rao Tummala, Professor and Director of NSF ERC at Georgia Institute of Technology, will present the keynote address on October 29. Professor Tummala is a Distinguished and Endowed Chair Professor, and Founding Director of NSF ERC at Georgia Tech. Past accolades include pioneering such major technologies as the first plasma flat panel display based on gas discharge, the first and next three generations of multichip packaging based on 35-layer alumina and 61-layer LTCC with copper and copper-polymer thin film, and materials for ink-jet printing and magnetic storage.
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A Message From Dr. Gilleo
“Wafer-Level Packaging (WLP) has been gathering momentum ever since we launched IWLPC in 2004. In fact, we've outgrown our venue and will be expanding into the Santa Clara Marriot for 2009. We won't be turning away exhibitors and we're expanding tech sessions with a 3rd track – MEMS WL and WLP. We hope to see you at IWLPC 2009. we're already hard at work to guarantee a bigger and better event.”
-Dr. Ken Gilleo, ET-Trends LLC
Conference General Chair
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Plans are underway for the 2009 program. Continue to check back here for developing information and contact Melissa Serres Marx or Leslee Johns with any questions in the meantime.
IWLPC 2009 Sponsors
Gold Sponsors
Silver Sponsor
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