Advanced Packaging in the New Connected World
October 22 - 24, 2019
DoubleTree by Hilton San Jose
San Jose, California, USA

Professional Development Courses (PDCs)

Thursday, October 25, 2018

The IWLPC courses are application-oriented and structured to combine field experience with scientific research to solve everyday problems.

  • PDC1 - Fan Out Packaging – Technology Evolution
  • PDC2 - Modeling failure modes for Chip Package Interactions and Package Level Reliability
  • PDC3 - Fan-Out Wafer/Panel-Level Packaging for 3D IC Heterogeneous Integration
  • PDC4 - Polymers and Processes Used in Wafer Level Packaging

  • PDC1

    Fan Out Packaging – Technology Evolution

    John Hunt John Hunt, ASE (US) Inc.
    October 25, 2018
    8:30am–12:00pm | San Carlos

    This course will review how the integration of a wide variety of packaging technologies, wafer level processing, substrate evolution and Flip Chip packaging structures have come together into 2D and 3D Fan Out packages. It will further explore the higher levels of integration and sophistication using Fan Out as a basic manufacturing technology, describing the evolving functionality and complexity achieved by combining low cost materials and innovative process flows. By using such combinations of tools and processes, the resulting packages are evolving into increasingly complex structures for both low density mobile and higher density server applications

    1. Background
        a. Bumping
        b. WLCSP
    2. Brief History of Fanout
        a. Early Contributors
    3. What is Fan Out
    4. Drivers for Fan Out
        a. Historical Drivers
        b. Advanced Drivers
    5. Advantages of Fan Out
    6. Fan Out Market Forecast
    7. 2D Fan Out Structures
        a. Low Density 2D Fan Out
        b. High Density 2D Fan Out
    8. Fan Out System in Package (SiP)
        a. Passive Components in Fan Out
        b. Fan Out alternatives for SiP
    9. 3D Fan Out Structures
        a. 3D Interconnectivity Structures
        b. Low Density 3D Fan Out
        c. High Density 3D Fan Out
    10. Discussion of Processes & Structures
        a. Potential Processing Issues
        b. Specific Structures & Processes
        c. Comparison of Fan Out Technologies
    11. Reliability Considerations
        a. Reliability Factors
    12. Panel Fan Out
        a. Drivers
        b. Considerations

    Who Should Attend?
    Engineers, managers, and purchasing individuals who want to understand the basics and variety of options available using Fan Out packaging technologies.


    Modeling failure modes for Chip Package Interactions and Package Level Reliability

    Gil Sharon Gil Sharon, DfR Solutions
    October 25, 2018
    8:30am–12:00pm | San Martin

    This course will cover prediction methodologies for flip chip die and package level reliability. The mechanical process for several failure modes will be discussed with examples of die cracking, bump fatigue, white bump, package warpage, board level reliability and microvia failures. Modeling methodologies for each of the failure modes will be shown. Possible mitigation strategies and options at the package level will be explored. The physical and mechanical processes of attaining reliability are an integral part of this course. Participants are expected to have a basic knowledge of BGA, QFN and Package-on-Package structures. Participants should also be familiar with finite element modeling and analysis methods.

    Modeling failure modes for Chip-package interactions and package level reliability
    1. Introduction to flip chip packaging (45 minutes)
    2. Common failure modes in flip chip packages (60 minutes)
    3. Modeling methods and considerations for each failure mode (60 minutes)
    4. Mitigation strategies for different failure modes (45 minutes)
    5. Discussion on trade offs in chip-package interactions (30 minutes)

    Common Failure modes:

  • Die cracking during chip attach
  • White bump and ELK stress
  • C4 SnAg bump fatigue
  • Predicting package warpage
  • Via failures (copper fatigue and via delamination)
  • Board level reliability and BGA/QFN solder fatigue

    Who Should Attend?
    This course is directed towards the fabless semiconductor manufacturing segment. Participants should be involved in design, manufacturing or purchasing of flip chip packaging services. This course will be especially helpful to device manufacturers and designers.



    Fan-Out Wafer/Panel-Level Packaging for 3D IC Heterogeneous Integration

    Dr. John H. Lau John Lau, Ph.D., ASM Pacific Technology
    October 25, 2018
    1:30pm-5:00pm | San Carlos

    Because of the drive of Moore's law, SoC (system-on-chip) has been very popular in the past 10+ years. Unfortunately, the end of Moore's law is fast approaching and it is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC. Heterogeneous integration contrasts with SoC. Heterogeneous integration uses packaging technology to integrate dissimilar chips with different functions into a system or subsystem. For the next few years, we will see more implementations of a higher level of heterogeneous integration, whether it is for time-to-market, performance, form factor, power consumption or cost. Fan-out wafer-level packaging (FOWLP) has been getting lots of tractions since TSMC used their FOWLP to package the application processor for the iPhone 7. In this lecture, the following topics will be presented and discussed. Emphasis is placed on the latest developments of these areas in the past three years. Their future trends will also be explored.

    [1] Introduction
    [2] Formation of Fan-out Wafer-Level Packaging (FOWLP)
         FOWLP Chip-first (die face-down)
         FOWLP Chip-first (die face-up)
         FOWLP Chip-last (RDL-first)
    [3] Fabrication of Redistribution Layers (RDLs)
         Polymer and ECD Cu + Etching
         PECVD and Cu Damascene + CMP
         Hybrid RDLs
    [4] TSMC InFO-WLP and InFO-PoP
    [5] Formation of Fan-out Panel-Level Packaging (FOPLP)
         PCB + SAP
         PCB + LDI
         PCB + TFT-LCD
         PCB/ABF/SAP + LDI
         SEMCO PLP
    [6] Wafer vs. Panel
         Application Ranges of FOWLP and FOPLP
         Critical Issues of FOPLP
    [7] Embedded Chips Panel-Level Packaging (ECP)
    [8] Trends in FOWFP and FOPLP
    [9] System-on-Chip (SoC)
         Apple's Application Processor (A10)
         Apple's Application Processor (A11)
    [10] Heterogeneous Integration vs. SoC
    [11] Heterogeneous Integration on Organic Substrates (SiP)
         Amkor's SiP for Automobiles
         Apple Watch II Assembled by ASE
         Intel's Knights-Landing with Micron's HMC on Organic Substrate
         Cisco/eSilicon's Networking System on Organic Interposer
    [12] Heterogeneous Integration on Silicon Substrates (TSV-Interposers)
         Leti's System-on-Wafer (SoW)
         UCLA's SoW
         TSMC/Xilinx's CoWoS
         TSMC's CoWoS-2
         AMD's GPU with Hynix's HBM and UMC's TSV-interposer
         NVidia's GPU with Samsung's HMB2 and TSMC's TSV-interposer
         AMD's GPU/CPU Chiplets on TSV-interposers
    [13] Heterogeneous Integration on RDLs and/or TSV-less Interposers
         Xilinx/SPIL's TSV-less SLIT
         SPIL/Xilinx's TSV-less NTI
         Amkor's TSV-less SLIM
         Amkor's TSV-less SWIFT
         Amkor's TSV-less SLIM with FOWLP
         SPIL's TSV-less FOWLP with Hybrid RDLs
         STATS ChipPac's FOFC eWLB
         ASE's TSV-less FOCoS
         MediaTek's TSV-less RDLs by FOWLP
         Intel's TSV-less EMIB
         Intel/AMD's TSV-less EMIB for CPU, GPU, and HBM
         3D IC Heterogeneous Integration for Application Processor Chipset
         3D IC High-Performance Heterogeneous Integration
         Samsung's Heterogeneous Integration on RDLs for Mobile Applications
         Samsung's Heterogeneous Integration on RDLs for high-end applications
         Assembly of Heterogeneous Integration
    [14] Heterogeneous Integration Trends
    [15] Q&A

    Who Should Attend
    If you (students, engineers, and managers) are involved with any aspect of the electronics and optoelectronic industry, you should attend this course. It is equally suited for R&D professionals and scientists.


    Polymers and Processes Used in Wafer Level Packaging

    Jeffrey Gotro, Ph.D. Jeffrey Gotro, Ph.D., InnoCentrix, LLC
    October 25, 2018
    1:30pm-5:00pm | San Martin

    The course will provide an overview of polymers and the important structure-property-process-performance relationships for polymers used in wafer level packaging. The main learning objectives will be: 1) understand the types of polymers used in wafer level packages, including underfills (pre-applied and wafer applied), mold compounds, and substrate materials 2) gain insights on how polymers are used in Fan Out Wafer Level Packaging, specifically mold compounds and polymer redistribution layers (RDL) 3) learn the key polymer and processes challenges in Fan Out Wafer Level Packaging.

    Course Outline

  • Overview of polymers used in Wafer Level Packaging
  • Epoxy Mold compounds
  • Photosensitive polyimides and polybenzoxazoles
  • Pre-applied underfills and wafer level underfills, chemistry and process
  • High density substrate materials including coreless substrates
  • Polymer challenges in Fan-out wafter level packaging
  • Wafer versus panel processing; polymer challenges and solutions

    Who Should Attend?
    Packaging engineers involved in the development, production, and reliability testing of electronic packages would benefit. Those interested in gaining an understanding of the role of polymers and polymer-based processes used in wafer level packaging will also find this short course valuable.

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    Organized by: SMTA and ChipScale Review

    Supported by:
    IEEE Electronic Packaging Society Panel Level Packaging Consortium

    Supporting Media:
    MEPTEC Open Sky Communications