International Wafer-Level Packaging Conference Call for Papers
The SMTA and Chip Scale Review magazine are pleased to announce plans for the 7th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition (IWLPC). This premier industry event explores leading-edge design, material, and process technologies being applied to Wafer-Level Packaging applications. There will be special emphasis on the numerous device and end product applications (RF/wireless, sensors, mixed technology, optoelectronics) that demand wafer level packaging solutions for integration, cost, and performance requirements.
The IWLPC Technical Chair, Lee Smith of Amkor Technology, and the IWLPC Technical Committee would like to invite you to submit an abstract for this program. Deadline for submittal is April 23, 2010.
The conference includes three tracks with two days of papers covering: Wafer Level Packaging; 3-D (Stacked) Packaging; and MEMS Packaging.
Wafer Level Packaging:
Wafer Level Chip Scale Packaging (WLCSP),
Flip Chip Bumping
Fan-Out and Redistribution
Markets and Trends
Metrology and Testing
Wafer and Device Cleaning
WL-Enabled Devices
Nanotechnology
Quality, Reliability, and COO
MEMS Packaging:
MEMS Processes and Materials
MEMS Design Tools or Methods
Nano-MEMS and Bio-MEMS
MOEMS Integration
Lab-on-Chip
3-D Integration:
3D WLP
Thru Silicon Vias (TSV)
Silicon Interposers
Wafer Thinning and Handling
Stacking Processes (W2W,D2W,D2D)
IC Packaging Substrate
SIP/SOP vs. SOC
Mixed Chip Integration Issues
Embedded Die and Passives
Modeling & Simulation Tools and Methods
TSV Integration: FEOL vs BEOL
Metrology and Testing
Reliability and Inspection
We would be pleased to have you submit an abstract for this program. 200-300 word abstracts should be submitted on-line or by email to Melissa Serres melissa@smta.org. Please include a title, author name, and contact information with your abstract. Authors will be notified of acceptance in May 2010. Note that technical papers are required and will be due in August 2010.
