Bridging the Interconnect Gap
October 24 - 26, 2017
DoubleTree by Hilton San Jose
San Jose, California, USA

Call for Papers

International Wafer-Level Packaging Conference

The SMTA and Chip Scale Review are pleased to announce plans for the 14th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition. This premier industry event explores leading-edge design, material, and process technologies being applied to Wafer-Level Packaging applications. There will be special emphasis on the numerous device and end product applications (RF/wireless, sensors, mixed technology, optoelectronics) that demand wafer level packaging solutions for integration, cost, and performance requirements.

The IWLPC Technical Committee would like to invite you to submit an abstract for this program.
Abstract Deadline: April 10th, 2017

IMPORTANT: Please be sure to obtain approval to both write and present your paper prior to submitting an abstract. When a paper is accepted by the Technical Committee, it is our expectation that you have budget approval for travel costs and conference registration which is required for speakers.

The conference includes three tracks with two days of technical paper presentations covering: Wafer-Level Packaging; 3D (Stacked) Packaging; and MEMS Packaging. Also we will offer professional development courses.

Wafer-Level Packaging:
  • Wafer-Level Chip Scale Packaging (WLCSP)
  • Flip Chip Bumping
  • Fan-Out and Redistribution
  • Wafer and Device Cleaning
  • WL-Enabled Devices
  • Nanotechnology
  • Quality, Reliability, and COO

MEMS Packaging:
  • MEMS Processes and Materials
  • MEMS Design Tools or Methods
  • Nano-MEMS and Bio-MEMS
  • MOEMS Integration
  • Lab-on-Chip
  • MEMS Integration and Interconnects
  • RF/wireless, sensors, mixed technology, optoelectronics

New Manufacturing Challenges Sub-track added!
  • Quality and yield
  • Equipment throughput
  • Processing and equipment control (SPC, APC, FDC)
  • Factory output & cycle time
  • Materials
  • Automation
  • Logistics

  • 3D Package Integration:
    • 3D WLP
    • Thru Silicon Vias (TSV)
    • Silicon Interposers
    • Stacking Processes (W2W, D2W, D2D)
    • IC Packaging Substrate
    • Embedded Die and Passives
    • Modeling & Simulation Tools and Methods
    • TSV Integration: FEOL vs BEOL
    • Chip to Chip Optical Connection

    If you would like to present at this conference, please submit a 200-300 word abstract. Please include a title, author name, and contact information with your abstract.
    Note that technical papers are required and will be due September 4th, 2017.

    For more information on the conference, exhibition, or sponsorship opportunities, please contact Jenny Ng at or 952-920-7682.

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    Organized by SMTA and ChipScale Review

    Supported by:
    MEMS Journal MEPTEC MCA Public Relations Roger Grace Associates Yole Developpment