Bridging the Interconnect Gap
October 24 - 26, 2017
DoubleTree by Hilton San Jose
San Jose, California, USA

About IWLPC

IWLPC brings together the semiconductor industry’s most respected authorities to address all aspects of wafer-level, 3D, TSV, and MEMS device packaging technologies.

Addressing wafer-level packaging, 3D, and MEMS technologies, the International Wafer-Level Packaging Conference (IWLPC) has been at the forefront of packaging technology evolution. The conference has a rich history of bringing together attendees from over 16 countries in the heart of Silicon Valley to immerse themselves in the latest technology and business trends. Going into its 14th year, the IWLPC is co-produced by Chip Scale Review, the leading international magazine addressing the semiconductor packaging industry, and SMTA, the distinguished global association representing electronic assembly and manufacturing professionals.

The conference comprises three parallel technical tracks with two full days of presentations on wafer-level packaging, 3D integration, and MEMS development. Workshops, keynote speakers, and panel discussions are offered by world-class experts and enable attendees to broaden their technical knowledge. The technical program includes a two-day expo where 60+ exhibitors showcase their latest technologies and products. The conference provides a collective network of over 800 industry professionals, including vendors from leading semiconductor companies, foundries, and OSATs, as well as key technology, equipment, and materials suppliers in the exhibit area. Attendees will be inspired by the quantity and quality of the featured new developments and emerging technologies.



3D Integration Track

3D integration and interposer technology are now well accepted approaches for fabrication of high-performance memory-enhanced products, memory-on-logic stacks, and 3D IC products that are entering the market. Along with the above developments, 3D integration is also recognized as a key technology for heterogeneous devices that demand smart system integration, rather than extreme high-interconnect densities. Heterogeneous integration technologies are being developed for functional diversification systems, including the integration of CMOS-based devices with others, such as analog/RF, solid-state lighting, HV power, passives, sensors/actuators, biochips and biomedical devices. This heterogeneous integration started with system-in-packaging technology, and is expected to evolve into 3D heterogeneous integration with TSVs and wafer bonding. Many R&D activities worldwide are focusing on heterogeneous integration for novel functionalities. Corresponding 3D integration technologies are being evaluated at several companies, research institutions and industrial-driven research consortia (e.g., Hybrid Memory Cube, e-BRAINS, etc). Furthermore, there are significant advances for integrated MEMS systems using 3D integration technologies. The multitude of abstracts submitted to the IWLPC Technical committee is evidence of the wide array of activities and broad interest on in the subject matter.



WLP Track

Since its inception, the IWLPC has been at the forefront of technology evolution in wafer-level packaging (WLP) by addressing the material, process, equipment, and reliability challenges associated with these products. Over the years, the IWLPC has showcased the tremendous advancements in dielectric materials, photolithography techniques, and plating processes that have enabled wafer-level packaging to become the fasted growing IC packaging technology in the industry. These developments have also led to improved process capabilities and enhanced reliability for fan-out wafer-level products. Recently, the WLP Track expanded its scope for fan-out wafer-level packaging (FO-WLP) to accommodate the tremendous uptick in growth and interest on the part of the equipment and material suppliers, assembly providers, and end users.



MEMS Track

Wafer-level and 3D packaging process technologies are maturing and beginning to shape the fabrication trends of MEMS products. For example, cap wafer bonding has long been applied to hermetically isolate and protect sensitive MEMS transducers from the environment for improved performance and reliability. This development set the stage for early WLP integration of active wafer-to-wafer (W2W) bonding techniques that can provide improved MEMS performance tuning and size reduction through the addition of signal interconnect options between the CMOS and MEMS device. The first session of the MEMS track will demonstrate growing product examples using 3D MEMS package integration technologies such as W2W, chip-to-wafer (C2W), through-silicon via (TSV) interconnects, and hermetic wafer-level sealing.





Home | Top

Organized by: SMTA and ChipScale Review



Supported by:
MEMS Journal MEPTEC