Silicon to Systems
October 24 - 26, 2017
DoubleTree by Hilton San Jose
San Jose, California, USA

NEW! Interactive Presentations (Posters)

Tuesday, October 18

10:00am-1:30pm

Stop by and learn current research, case histories and projects from authors through Interactive Presentations. Interact with authors directly on topics on 3D, Manufacturing Challenges, MEMS and WLP.


Presentation will include:

Bridging the Gap: A Cohesive Design to Sign-off Platform for Wafer-Level Packaging
John Ferguson, Mentor Graphics

Performance Limits of Stacked FO WLPs and their Mitigation
Dev Gupta, APSTL

High-Performance, Low-Cost Photoresist Strip for Advanced Packaging Applications
George Chiaverini, Veeco Precision Surface Processing, and Amy Lujan, SavanSys Solutions LLC

Novel WLCSP Technology Solution for Fusion Device of CMOS Integrated Circuit with MEMS
Takahide Murayama, ULVAC, Inc.

Laminatable Positive-Tone Photosensitive Polyimide
Masao Tomikawa, Ph.D., Toray Industries, Inc.

Board Level Reliability of Automotive eWLB (Embedded Wafer-Level BGA)
Seung Wook Yoon, STATS ChipPAC Pte Ltd.

Study on a Formulated Flux for Ultra-Fine Flip Chip Interconnect
Hsiang Chuang Chen, SHENMAO America, Inc.





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Organized by: SMTA and ChipScale Review



Supported by:
MEMS Journal MEPTEC