October 24 - 26, 2017
DoubleTree by Hilton San Jose
San Jose, California, USA
SMTA and Chip Scale Review are pleased to announce the 14th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition. IWLPC brings together some of the semiconductor industry's most respected authorities addressing all aspects of wafer-level, 3D, TSV, and MEMS device packaging and manufacturing.
Learn more about why you should attend the 2017 IWLPC!
Submit an abstract for IWLPC 2017!
If you would like to present at this conference, please submit a 200-300 word abstract by April 10, 2017. Please include a title, author name, and contact information with your abstract. Technical papers and presentations are required and will be due September 8, 2017.
Click here to submit an abstract!
Thank you for attending IWLPC 2016!
The 13th International Wafer-Level Packaging Conference (IWLPC) and Exhibition, held in Silicon Valley on October 18-20, offered an excellent insight into current issues and future challenges in advanced packaging technologies. An impressive array of 48 presentations, five interactive presentations (poster sessions), and four workshops covered a wide array of topics with focus on various aspects of fan-out wafer-level packaging (FOWLP), 3D packaging and manufacturing, and microelectromechanical systems (MEMS). Overall, attendance was higher than what I’ve seen in past years, and the expo hall was sold out completely. Table-top exhibitors, who couldn’t get space inside the main exhibition hall, lined up their display items along the walkways in front of the main exhibit area. Quite fittingly, the main theme of the conference was “Bridging the Interconnect Gap,” thus highlighting one of the major challenges our industry is facing as "big data" seeps into our daily lives in multiple forms at the workplace, home, and in between.
Click here to read the full review!
Photos from IWLPC 2016