October 24 - 26, 2017
DoubleTree by Hilton San Jose
San Jose, California, USA
SMTA and Chip Scale Review are pleased to announce the 14th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition. IWLPC brings together some of the semiconductor industry's most respected authorities addressing all aspects of wafer-level, 3D, TSV, and MEMS device packaging and manufacturing.
Best Presentation & Papers Awards for 2016 Announced
The IWLPC Technical Committee is pleased to announce the Best of Conference, Best Presentation & Best Papers in WLP, 3D, MEMS and Manufacturing tracks as chosen by the technical committee and attendees based on technical merit, relevance, originality, knowledge of subject, quality of material, and quality of presentation.Best of Conference Presentation - Paul Silvestri, Amkor Technology
"TSV Assembly: Package Architectures and Trade-offs"
Best of Conference Paper - Allan Hilton, Micross Advanced Interconnect Technology
"Wafer-Level Vacuum Packaging of Microbolometer-based Infrared Imagers"
Best of 3D Track Paper - Min Tao, Ph.D. Invensas
"Package-On-Package Interconnect For Fan-Out Wafer Level Packages"
Best of WLP Track Paper - Stream Chung, Chemleader
"Electroplated Nano Twinned Copper for Wafer-Level Package"
Best of MEMS Track Paper - Allan Hilton, Micross Advanced Interconnect Technology
"Wafer-Level Vacuum Packaging of Microbolometer-based Infared Imagers"
Best of Manufacturing Track Paper - Gerard John, Amkor Technology
"A Practical Approach to Test Through-Silicon Vias (TSV)"
Learn more about why you should attend the 2017 IWLPC!
Submit an abstract for IWLPC 2017!
If you would like to present at this conference, please submit a 200-300 word abstract by May 1st, 2017. Please include a title, author name, and contact information with your abstract. Technical papers and presentations are required and will be due September 8, 2017.