International Wafer-Level Packaging Conference
October 11-14, 2010
The Package for Success!
Join the expanded three-track program of the IWLPC as it brings together some of the semiconductor industry's most respected international authorities who will address all aspects of wafer-level, 3D IC, and MEMS device packaging in an impressive four-day program.
Sponsored jointly by the SMTA and
Chip Scale Review magazine, the annual IWLPC explores cutting edge topics in wafer-level packaging and IC/MEMS/MOEMS packaging, including 3D/Stacked/CSP/SiP/SoP and mixed technology packages.
General Chair Message
The organizing committee for this year's International Wafer Level Packaging Conference (IWLPC) has done an outstanding job in assembling some of the leading technical and business experts from within the electronics industry for the October event. The objective of the IWLPC is to provide a unique venue that brings together scientists, engineers, academia, manufacturing and business people from around the world to present and debate some of the latest and hottest packaging technologies.
The program includes three concurrent technical tracks covering 3D, MEMS, and Wafer Level Packaging. These tracks are complemented by several high profile keynote addresses, two panel discussions on 3D Packaging and WLP Supply & Demand, a large vendor exhibition, and a series of educational short courses. The program is sure to be one of the best ever.
-Andrew Strandjord, Pac Tech USA
Conference General Chair
