Silicon to Systems
October 24 - 26, 2017
DoubleTree by Hilton San Jose
San Jose, California, USA

IWLPC 2017

October 24 - 26, 2017
DoubleTree by Hilton San Jose
San Jose, California, USA

SMTA and Chip Scale Review are pleased to announce the 14th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition. IWLPC brings together some of the semiconductor industry's most respected authorities addressing all aspects of wafer-level, 3D, TSV, and MEMS device packaging and manufacturing.




Program Finalized and Registration Now Open!

Interconnecting Wafer-Level packaging, 3D packaging, Advanced Manufacturing and Test, the International Wafer-Level Packaging Conference (IWLPC) is at the forefront of the packaging technology evolution; it is one of the premier industry conferences. The Wafer-Level Packaging (WLP) track features sessions on materials, processes, design, and new technology like Fan-Out WLP. The 3D Packaging track features sessions on Heterogeneous Integration Enablement, materials and equipmeny, processing technologies, and Smart System Integration and Applications. The Advanced manufacturing track features sessions on test, productivity, inspection, and metrology.

Get details on the technical program!







Keynote Speakers Announced


Subramanian Iyer

Packaging without the Package:
A More Holistic Moore's Law

Subramanian Iyer, Ph.D.

Distinguished Chancellor's Professor
Electrical Engineering Department
University of California, Los Angeles

Richard (Kwang Wook) Bae

Samsung's FOPLP:
Beyond Moore

Richard (Kwang Wook) Bae

Vice President, Corporate Strategy & Planning
Samsung Electro-Mechanics

Han Byung Joon, Ph.D.

Innovative Packaging Technologies
Usher in a New Era for Integration Solutions

Han Byung Joon, Ph.D.

Chief Executive Officer
STATS ChipPAC

Get details!





Learn more about why you should attend the 2017 IWLPC!

IWLPC 2017 Conference Video



Best Presentation & Papers Awards for 2016 Announced

The IWLPC Technical Committee is pleased to announce the Best of Conference, Best Presentation & Best Papers in WLP, 3D, MEMS and Manufacturing tracks as chosen by the technical committee and attendees based on technical merit, relevance, originality, knowledge of subject, quality of material, and quality of presentation.

Best of Conference Presentation - Paul Silvestri, Amkor Technology
"TSV Assembly: Package Architectures and Trade-offs"

Best of Conference Paper - Allan Hilton, Micross Advanced Interconnect Technology
"Wafer-Level Vacuum Packaging of Microbolometer-based Infrared Imagers"

Best of 3D Track Paper - Min Tao, Ph.D. Invensas
"Package-On-Package Interconnect For Fan-Out Wafer Level Packages"

Best of WLP Track Paper - Stream Chung, Chemleader
"Electroplated Nano Twinned Copper for Wafer-Level Package"

Best of MEMS Track Paper - Allan Hilton, Micross Advanced Interconnect Technology
"Wafer-Level Vacuum Packaging of Microbolometer-based Infared Imagers"

Best of Manufacturing Track Paper - Gerard John, Amkor Technology
"A Practical Approach to Test Through-Silicon Vias (TSV)"







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Organized by: SMTA and ChipScale Review



Supported by:
MEMS Journal MEPTEC