Interconnecting WLP, MEMS & 3D Integration
October 13 - 15, 2015
DoubleTree San Jose Airport Hotel
San Jose, CA

IWLPC - Interconnecting WLP, MEMS & 3D Integration

SMTA and Chip Scale Review are pleased to announce the 12th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition. IWLPC brings together some of the semiconductor industry's most respected authorities addressing all aspects of wafer-level, 3D, TSV, and MEMS device packaging.

GLOBALFOUNDRIES, Director, Package Architecture & Customer Technology (PACT) Rama Alapati to Keynote IWLPC 2015

IWLPC Keynote Rama Alapati

High Density Fan-Out: Evolution or Revolution

Tuesday, October 13, 2015

Continued form factor and IO density scaling pressures have necessitated innovation in wafer level packaging technologies including High Density Fan-Out at leading edge Si nodes. A thorough analysis of the end applications reveal clear IO density envelopes for multi-die Fan-Out packages. Industry solutions of today are very fragmented, enabling disruption in the application space. Silicon Foundries entry in to the Fan-Out space also clearly highlights opportunities for value capture in this expanding package format. For traditional players in this field "collaborative competition" enables a new way of competing with the foundries and business models that enables this new paradigm are possible and viable.

Rama Alapati is leading the Packaging Product Management group with focus on delivering package differentiated solutions. Rama led the 3D TSV technology start-up in GLOBALFOUNDRIES Fab 8 for sub-20nm nodes. He was also responsible for sub-20nm CPI qualification until recently. Rama represents GLOBALFOUNDRIES in consortia like imec, SRC and SEMATECH to drive packaging focused research programs. Prior to joining GLOBALFOUNDRIES, Rama was with Micron Technology for 8 years first as an etch engineer focused on pitch doubling technology for sub-50nm NAND and later on as a assignee at imec focusing on 3D-IC and BEoL integration. Rama graduated with Master of Science (Honors) in chemical engineering from the University of Kansas, Lawrence and prior to that received his Bachelor of Technology degree with distinction from Osmania University in Hyderabad, India. Rama has 25 granted patents, more than 10 publications and more than 25 invention disclosures pending adjudication at the USPTO. Rama was awarded the 2014 SRC "Mahboob Khan" award for mentorship of graduate students

What You Are Saying About IWLPC

We have participated in the IWLPC for the last two years and have found that the technical presentations have been very enlightening. IMT being a MEMS foundry utilizes wafer level packaging in over 70% of the products that we produce and would not miss this important conference. We also found the exhibit hall experience very valuable.
-Michael Shillinger, Founder, Innovative Micro Technology (IMT)
The International Wafer Level Packaging Conference has consistently been an excellent venue for both its technical presentations and vendor exhibits. We have been attending the IWLPC for the last seven years and found it to be very valuable for both our people and company.
-Robert Marshall, RMM
IWLPC is the premier conference for emerging packaging technologies from the chip scale to the wafer scale. The conference brings together vendors, users and decision makers and is extremely valuable to EV Group.
-Garrett Oakes, Technology Director, EV Group
IWLPC brings visitors from around the world to a focused event that allows exchange of new developments and ideas.
-E. Jan Vardaman, President, TechSearch International, Inc.

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Organized by SMTA and ChipScale Review